Commit f2a40e26 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add basic HAL devices for the SPI controllers

Detail:
  s/SPI - Basic HAL devices for the 3 SPI controllers. These expose the register addresses & IRQ numbers, and (for SPI1 & SPI2) deal with enabling/disabling the hardware and the shared IRQ line. GPIO mapping currently isn't dealt with - we don't know which pin group to use (SPI0 can use two different sets on the compute) or how many chip select lines are desired.
  Makefile - Add SPI source
  hdr/BCM2835 - Add aux SPI registers
  hdr/StaticWS - Reserve workspace for the HAL devices
  s/Top - Register new devices in HAL_InitDevices
Admin:
  Tested on Raspberry Pi B & 2 B


Version 0.45. Tagged as 'BCM2835-0_45'
parent c059b1ca
......@@ -17,7 +17,7 @@
COMPONENT = BCM2835 HAL
TARGET = BCM2835
OBJS = Top CLib CMOS Debug Interrupts SDIO Stubs Timers UART USB Video DMA Messaging GPIO VCHIQ IIC RTC
OBJS = Top CLib CMOS Debug Interrupts SDIO Stubs Timers UART USB Video DMA Messaging GPIO VCHIQ IIC RTC SPI
HDRS =
CMHGFILE =
......
/* (0.44)
/* (0.45)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.44
#define Module_MajorVersion_CMHG 0.45
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 16 Feb 2015
#define Module_Date_CMHG 26 Jul 2015
#define Module_MajorVersion "0.44"
#define Module_Version 44
#define Module_MajorVersion "0.45"
#define Module_Version 45
#define Module_MinorVersion ""
#define Module_Date "16 Feb 2015"
#define Module_Date "26 Jul 2015"
#define Module_ApplicationDate "16-Feb-15"
#define Module_ApplicationDate "26-Jul-15"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.44"
#define Module_HelpVersion "0.44 (16 Feb 2015)"
#define Module_LibraryVersionInfo "0:44"
#define Module_FullVersion "0.45"
#define Module_HelpVersion "0.45 (26 Jul 2015)"
#define Module_LibraryVersionInfo "0:45"
......@@ -413,7 +413,14 @@ AUXMUSCRATCH * &5c ; MU Scratch reg
AUXMUCNTL * &60 ; MU extra control
AUXMUSTAT * &64 ; MU extra status
AUXMUBAUD * &68 ; MU Baud rate
; etc
AUXSPI0 * &80 ; Aux SPI0 (aka SPI1) base
AUXSPI1 * &C0 ; Aux SPI1 (aka SPI2) base
AUXSPICNTL0 * &0 ; Aux API control 0
AUXSPICNTL1 * &4 ; Aux SPI control 1
AUXSPISTAT * &8 ; Aux API status
AUXSPIIO * &10 ; Aux API data
AUXSPIPEEK * &14 ; Aux SPI PEEK
; UART TXD0 RXD0
......
......@@ -159,6 +159,9 @@ GPIODevice # HALDevice_GPIO_Size
VDUDevice # HALDevice_VDU_Size
VDUDevSpec # VDUDevSpec_Size
RTCDeviceStruct # 80
SPI0Device # HALDeviceSize
SPI1Device # HALDeviceSize
SPI2Device # HALDeviceSize
HAL_WsSize * :INDEX:@
sizeof_workspace * :INDEX:@
......
;
; Copyright (c) 2015, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
AREA |ARM$$code|, CODE, READONLY, PIC
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:Proc
GET Hdr:GPIODevice
GET hdr.BCM2835
GET hdr.StaticWS
EXPORT SPI_InitDevices
IMPORT memcpy
MACRO
$class HALDeviceField $field, $value
LCLS myvalue
[ "$value" = ""
myvalue SETS "$field"
|
myvalue SETS "$value"
]
ASSERT . - %A0 = HALDevice_$class$field
[ ?HALDevice_$class$field = 2
DCW $myvalue
ELIF ?HALDevice_$class$field = 4
DCD $myvalue
|
% ?HALDevice_$class$field
]
MEND
; Template for SPI devices
SPI0_Dev
0
HALDeviceField Type, HALDeviceType_Comms + HALDeviceComms_SPI
HALDeviceField ID, HALDeviceID_SPI_BCM2835_0
HALDeviceField Location, HALDeviceBus_Sys + HALDeviceSysBus_AHB + 0 ; Unit 0 = SPI0
HALDeviceField Version, 0
HALDeviceField Description, SPI0_Description
HALDeviceField Address, 0
HALDeviceField Reserved1, 0
HALDeviceField Activate, SPI0_Activate
HALDeviceField Deactivate, SPI0_Deactivate
HALDeviceField Reset, SPI0_Reset
HALDeviceField Sleep, SPI0_Sleep
HALDeviceField Device, iDev_GPU_SPI
HALDeviceField TestIRQ, 0
HALDeviceField ClearIRQ, 0
HALDeviceField Reserved2, 0
ASSERT . - %A0 = HALDeviceSize
SPI1_Dev
0
HALDeviceField Type, HALDeviceType_Comms + HALDeviceComms_SPI
HALDeviceField ID, HALDeviceID_SPI_BCM2835_12
HALDeviceField Location, HALDeviceBus_Sys + HALDeviceSysBus_AHB + 1 ; Unit 1 = SPI1
HALDeviceField Version, 0
HALDeviceField Description, SPI1_Description
HALDeviceField Address, 0
HALDeviceField Reserved1, 0
HALDeviceField Activate, SPI1_Activate
HALDeviceField Deactivate, SPI1_Deactivate
HALDeviceField Reset, SPI1_Reset
HALDeviceField Sleep, SPI1_Sleep
HALDeviceField Device, iDev_GPU_AuxInt + (1:SHL:31)
HALDeviceField TestIRQ, SPI1_TestIRQ
HALDeviceField ClearIRQ, 0
HALDeviceField Reserved2, 0
ASSERT . - %A0 = HALDeviceSize
SPI2_Dev
0
HALDeviceField Type, HALDeviceType_Comms + HALDeviceComms_SPI
HALDeviceField ID, HALDeviceID_SPI_BCM2835_12
HALDeviceField Location, HALDeviceBus_Sys + HALDeviceSysBus_AHB + 2 ; Unit 2 = SPI2
HALDeviceField Version, 0
HALDeviceField Description, SPI2_Description
HALDeviceField Address, 0
HALDeviceField Reserved1, 0
HALDeviceField Activate, SPI2_Activate
HALDeviceField Deactivate, SPI2_Deactivate
HALDeviceField Reset, SPI2_Reset
HALDeviceField Sleep, SPI2_Sleep
HALDeviceField Device, iDev_GPU_AuxInt + (1:SHL:31)
HALDeviceField TestIRQ, SPI2_TestIRQ
HALDeviceField ClearIRQ, 0
HALDeviceField Reserved2, 0
ASSERT . - %A0 = HALDeviceSize
SPI0_Description
= "BCM2835 SPI0 controller", 0
SPI1_Description
= "BCM2835 SPI1 controller", 0
SPI2_Description
= "BCM2835 SPI2 controller", 0
ALIGN
; Initialise our HAL devices
SPI_InitDevices ROUT
Entry
; SPI0 is always available
ADRL a1, SPI0Device
ADR a2, SPI0_Dev
MOV a3, #HALDeviceSize
BL memcpy
ADRL a2, SPI0Device
LDR a1, PeriBase
ADD a1, a1, #&204000
STR a1, [a2, #HALDevice_Address]
MOV a1, #0
MOV lr, pc
LDR pc, OSentries+4*OS_AddDevice
; SPI1 is available on the larger 40 pin header used on B+ and later
LDR a1, Board_Model
LDR a2, Board_Revision
CMP a1, #0
CMPEQ a2, #&10
EXIT LO
ADRL a1, SPI1Device
ADR a2, SPI1_Dev
MOV a3, #HALDeviceSize
BL memcpy
ADRL a2, SPI1Device
LDR a1, PeriBase
LDR a3, =AUXIO_Base+AUXSPI0
ADD a1, a1, a3
STR a1, [a2, #HALDevice_Address]
MOV a1, #0
MOV lr, pc
LDR pc, OSentries+4*OS_AddDevice
; SPI2 is currently only available on the Compute
LDR a1, Board_Model
LDR a2, Board_Revision
CMP a1, #0
CMPEQ a2, #&11
EXIT NE
ADRL a1, SPI2Device
ADR a2, SPI2_Dev
MOV a3, #HALDeviceSize
BL memcpy
ADRL a2, SPI2Device
LDR a1, PeriBase
LDR a3, =AUXIO_Base+AUXSPI1
ADD a1, a1, a3
STR a1, [a2, #HALDevice_Address]
MOV a1, #0
MOV lr, pc
LDR pc, OSentries+4*OS_AddDevice
EXIT
SPI0_Activate
MOV a1, #1
SPI0_Deactivate
SPI0_Reset
MOV pc, lr
SPI0_Sleep
MOV a1, #0
MOV pc, lr
SPI1_Activate
; Enable the controller
LDR a1, [a1, #HALDevice_Address]
DataSyncBarrier a3
LDR a2, [a1, #AUXEnables-AUXSPI0]!
ORR a2, a2, #2
STR a2, [a1]
DataSyncBarrier a3
MOV a1, #1
MOV pc, lr
SPI1_Deactivate
; Disable the controller
LDR a1, [a1, #HALDevice_Address]
DataSyncBarrier a3
LDR a2, [a1, #AUXEnables-AUXSPI0]!
BIC a2, a2, #2
STR a2, [a1]
DataSyncBarrier a3
MOV pc, lr
SPI1_Reset
MOV pc, lr
SPI1_Sleep
MOV a1, #0
MOV pc, lr
SPI1_TestIRQ
; Check the aux IRQ register
LDR a1, [a1, #HALDevice_Address]
LDR a1, [a1, #AUXIRQ-AUXSPI0]
MOV a1, a1, LSR #1
AND a1, a1, #1
DataSyncBarrier a3
MOV pc, lr
SPI2_Activate
; Enable the controller
LDR a1, [a1, #HALDevice_Address]
DataSyncBarrier a3
LDR a2, [a1, #AUXEnables-AUXSPI1]!
ORR a2, a2, #4
STR a2, [a1]
DataSyncBarrier a3
MOV a1, #1
MOV pc, lr
SPI2_Deactivate
; Disable the controller
LDR a1, [a1, #HALDevice_Address]
DataSyncBarrier a3
LDR a2, [a1, #AUXEnables-AUXSPI1]!
BIC a2, a2, #4
STR a2, [a1]
DataSyncBarrier a3
MOV pc, lr
SPI2_Reset
MOV pc, lr
SPI2_Sleep
MOV a1, #0
MOV pc, lr
SPI2_TestIRQ
; Check the aux IRQ register
LDR a1, [a1, #HALDevice_Address]
LDR a1, [a1, #AUXIRQ-AUXSPI1]
MOV a1, a1, LSR #2
AND a1, a1, #1
DataSyncBarrier a3
MOV pc, lr
END
......@@ -131,6 +131,8 @@
IMPORT RTC_InitDevices
IMPORT SPI_InitDevices
IMPORT HAL_SendHostMessage
IMPORT HAL_QueryPlatform
......@@ -787,6 +789,7 @@ HAL_InitDevices
BL GPIO_InitDevices
BL VCHIQ_InitDevices
BL RTC_InitDevices
BL SPI_InitDevices
LDR pc, [sp], #4
......
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