Add BCM memory barriers

The BCM2711 manual suggests that yes, the BCM2835-style memory barriers
are still needed when accessing peripherals

s/IntVC6

@@ -150,8 +150,6 @@ GICtoOS
 ; and the extended GPU IRQs in the range >= iDev_Ext_Base+32 are inaccessible.
 ; However we do have control over the FIQ bypass, so by leaving that enabled we
 ; can access FIQs via the new BCM2838 FIQ controller.
-;
-; TODO - Do we still need BCM2835-style memory barriers?
 
 MAX_FIQ * iDev_ARM_MiscGPU1
 
@@ -165,6 +163,7 @@ InterruptVC6_Init ROUT
         STR     v1, GICD_Base_Address
         ADD     v2, a1, #GICC_Base
         STR     v2, GICC_Base_Address
+        DataSyncBarrier ip
         ; Disable distributor while we fiddle with it
         MOV     a1, #0
         STR     a1, [v1, #GICD_CTLR]
@@ -211,6 +210,8 @@ InterruptVC6_Init ROUT
         MOV     a1, #1
         STR     a1, [v1, #GICD_CTLR]
 
+        DataSyncBarrier ip ; Switching peripheral
+
         ; Configure CPU interface
         MOV     a1, #&FF
         STR     a1, [v2, #GICC_PMR] ; Highest PMR value = any priority interrupt will pass the test
@@ -221,6 +222,7 @@ InterruptVC6_Init ROUT
         ; - FIQBypDisGrp1 is left at zero so that the bypass is enabled, allowing us to get FIQs from the BCM2838 FIQ controller
         MOV     a1, #1
         STR     a1, [v2, #GICC_CTLR]
+        DataSyncBarrier ip
         EXIT
 
 ;
@@ -252,6 +254,7 @@ VC6_HAL_IRQEnable ROUT
         ADD     a4, a4, #GICD_ISENABLER
         MOV     a3, ip, LSL a3
         LDR     a1, [a4, a2, LSL #2] ; Get old state
+        DataSyncBarrier ip           ; After last read, before first write
         STR     a3, [a4, a2, LSL #2] ; Enable
         AND     a1, a1, a3
         MOV     pc, lr
@@ -261,6 +264,7 @@ VC6_HAL_IRQDisable ROUT
         BHS     ExitZero
         LDR     a4, GICD_Base_Address
         OStoGICBitno a2, a3, a1
+        DataSyncBarrier ip
         MOV     ip, #1
         ADD     a4, a4, #GICD_ICENABLER
         MOV     a3, ip, LSL a3
@@ -279,11 +283,12 @@ VC6_HAL_IRQDisable ROUT
         AND     a2, a2, #3
         LDR     a1, [a1, a2, LSL #2]
 80
+        DataSyncBarrier ip ; Switching peripheral
         LDR     a2, GICC_Base_Address
         STR     a1, [a2, #GICC_EOIR]
 90
         AND     a1, ip, a3
-        DSB     SY
+        DataSyncBarrier ip
         MOV     pc, lr
 
 VC6_HAL_IRQClear ROUT
@@ -297,6 +302,7 @@ VC6_HAL_IRQClear ROUT
         AND     ip, ip, #3
         LDR     a1, [a1, ip, LSL #2]
 10
+        DataSyncBarrier ip           ; After last read, before first write
         STR     a1, [a4, #GICC_EOIR]
         DSB     SY        
         MOV     pc, lr
@@ -304,6 +310,7 @@ VC6_HAL_IRQClear ROUT
 VC6_HAL_IRQSource ROUT
         LDR     a4, GICC_Base_Address
         LDR     a2, [a4, #GICC_IAR]
+        DataSyncBarrier ip
       [ GICDebug
         Push    "lr"
         BL      HAL_DebugTXStrInline
@@ -341,6 +348,7 @@ VC6_HAL_IRQStatus ROUT
         ADD     a4, a4, #GICD_ISPENDR
         LDR     a1, [a4, a2, LSL #2]
         AND     a1, ip, a1, LSR a3
+        DataSyncBarrier ip
         MOV     pc, lr
 
 ;
@@ -481,6 +489,7 @@ VC6_HAL_IRQSetCores ROUT
         OStoGICNumber a1, ip
         ADD     a4, a4, a1
         AND     a1, a2, #&F
+        DoMemBarrier ip
         STRB    a1, [a4, #GICD_ITARGETSR]
         MOV     pc, lr
 
@@ -494,6 +503,7 @@ VC6_HAL_IRQGetCores ; read-only version of IRQSetCores
         OStoGICNumber a1, ip
         ADD     a4, a4, #GICD_ITARGETSR
         LDRB    a1, [a4, a1]
+        DoMemBarrier ip
         MOV     pc, lr
 80
         ; PPI