Commit c892a3f3 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

8GB RAM support

Update OS_AddRAM sequence to detect 8GB Pi models and register the extra
RAM bank.

Also, remove the software RAM clear code; it won't work for clearing RAM
above the 4GB barrier, and (for a software RAM clear) it's quicker for
the kernel to clear the RAM itself (since it'll do it with the
MMU/caches enabled, and will do it in parallel with the keyboard scan).
E.g. for a 4GB Pi, the time between the HalStartup debug message (prior
to HAL RAM clear) and ModuleInit debug message (after kernel RAM clear)
used to be 1124cs, but is now 636cs. For an 8GB Pi the time is 948cs.

Version 0.94. Tagged as 'HAL_BCM2835-0_94'
parent 8aaf0511
/* (0.93)
/* (0.94)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.93
#define Module_MajorVersion_CMHG 0.94
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 16 Dec 2020
#define Module_Date_CMHG 17 Mar 2021
#define Module_MajorVersion "0.93"
#define Module_Version 93
#define Module_MajorVersion "0.94"
#define Module_Version 94
#define Module_MinorVersion ""
#define Module_Date "16 Dec 2020"
#define Module_Date "17 Mar 2021"
#define Module_ApplicationDate "16-Dec-20"
#define Module_ApplicationDate "17-Mar-21"
#define Module_ComponentName "HAL_BCM2835"
#define Module_FullVersion "0.93"
#define Module_HelpVersion "0.93 (16 Dec 2020)"
#define Module_LibraryVersionInfo "0:93"
#define Module_FullVersion "0.94"
#define Module_HelpVersion "0.94 (17 Mar 2021)"
#define Module_LibraryVersionInfo "0:94"
......@@ -417,7 +417,7 @@ relocate_10
; code to execute. Move them into a holding space in the relocated ROM
; so that we don't break them when we overwrite the boot stub.
CPUDetect lr
BCC clear_ram
BCC cores_idle
LDREQ a1, =INT_BASE_BCM2836
LDRHI a1, =INT_BASE_BCM2838
MVN a2, #0
......@@ -436,7 +436,7 @@ relocate_10
MOV a4, #QA7_CORE0_MBOX1_RDCLR
10
SUBS a3, a3, #1
BEQ %FT20
BEQ cores_timeout
LDR a2, [a1, a4]
CMP a2, #0
BEQ %BT10
......@@ -447,41 +447,17 @@ relocate_10
BL HAL_DebugTXStrInline
DCB "Aux cores in holding pattern", 10, 0
ALIGN
B %FT25
B cores_idle
]
20
cores_timeout
[ HALDebug
BL HAL_DebugTXStrInline
DCB "Failed waking cores", 10, 0
ALIGN
25
]
cores_idle
clear_ram
; Clear RAM
; v3 is start of RAM
; ip is end of RAM/start of ROM
; Note this code will clear the stack, but there shouldn't be anything on it yet anyway
MOV a1, ip
LDR v2, ARM_Base2
MOV a2, #0
MOV a3, #0
MOV a4, #0
MOV v1, #0
MOV v4, #0
MOV v5, #0
MOV v7, #0
MOV lr, #0
clear_lp1
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
TEQ a1, v2
LDREQ a1, ARM_End
CMP a1, v3
BHI clear_lp1
MOV a1, #0 ; AddRAM reference handle (NULL for first call)
Push "a1, ip"
LDR a2, ARM_Base
......@@ -496,13 +472,13 @@ clear_lp1
BL HAL_DebugHexTX4
MOV a1, a3
BL HAL_DebugHexTX4
MOV a1, #0
]
MOV a1, #0
MVN a4, #0
CallOSM OS_AddRAM
STR a1, [sp] ; ref for next call
MOV a1, #0
; Second RAM chunk? (Pi 4)
LDR a2, ARM_Base2
LDR a3, [sp, #4]
CMP a3, a2
......@@ -515,13 +491,38 @@ clear_lp1
BL HAL_DebugHexTX4
MOV a1, a3
BL HAL_DebugHexTX4
MOV a1, #0
]
MOV a1, #0
MVN a4, #0
CallOSM OS_AddRAM
STR a1, [sp] ; ref for next call
01
; Third RAM chunk? (8GB Pi 4)
LDR a1, Board_Revision
TST a1, #BoardRevision_NewScheme
BEQ %FT02
AND a1, a1, #BoardRevision_Mem_Mask
CMP a1, #BoardRevision_Mem_8G
BNE %FT02
MOV a2, #1<<20 ; 4GB in 4K units
MOV a3, #2<<20 ; 8GB in 4K units
[ HALDebug
BL HAL_DebugTXStrInline
DCB "HalStartup5 .. rst rend",10,0
ALIGN
MOV a1, a2
BL HAL_DebugHexTX4
MOV a1, a3
BL HAL_DebugHexTX4
]
MOV a1, #OSAddRAM_LargeAddresses
MVN a4, #0
CallOSM OS_AddRAM
STR a1, [sp] ; ref for next call
02
; OS kernel informed of RAM areas
LDR a2, PeriBase
......@@ -530,7 +531,7 @@ clear_lp1
TST a2, #PM_RSTS_HADPOR
Pull "a4,ip" ; a4 = ref from last AddRAM
MOV a1, #OSStartFlag_RAMCleared
MOV a1, #0
ORRNE a1, a1, #OSStartFlag_POR
ADRL a2, HAL_Base + OSROM_HALSize ; a2 -> RISC OS image
CPUDetect a3
......
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