Commit c6f51390 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL

DMA improvements & fixes

* Update DMA & DMA lite channels to work on Pi 4 (HAL_IRQClear calls
needed)
* Fix DMAL_Abort / DMAL_Reset to reset the channel properly (register
muddle meant the old reset code wasn't doing anything - and wasn't a
particularly great way of resetting anyway)
* Fix DMAL_CurtailListTransfer not working very well
* Fix IRQ mapping of channels 11-14, allowing channels 12-14 to be used
* Implement support for Pi 4 DMA4 channels. On Pi 4 these are the only
channels we'll bother using, since DMA & DMA lite have annoying
restrictions on accessing RAM above 1GB
parent de19ec44
......@@ -466,8 +466,7 @@ ARM_Timer_Base * &0000b400 ; base of ARM timer regs
; DMA registers
DMA_Base * &00007000
; DMA_CH_Count * 13 ; Allegedly 16 channels, but can only get IRQs from 13 of them?
DMA_CH_Count * 12 ; Was 13, but firmware bug is incorrectly reporting that ch 12 is available
DMA_CH_Count * 15 ; 16 channels, but one permanently reserved for GPU
; Message-based parallel host interface
MPHI_Base * &00006000
......@@ -612,9 +611,9 @@ iDev_GPU_DMA9 * 25 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_0 * 25 ; BCM2838
iDev_GPU_DMA10 * 26 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_1 * 26 ; BCM2838
iDev_GPU_DMA11 * 27 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA11_14 * 27 ; channels 11-14 shared IRQ, BCM2835-7
iDev_GPU_DMA40_2 * 27 ; BCM2838
iDev_GPU_DMA12 * 28 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA * 28 ; "unused shared IRQ for all channels", BCM2835-7
iDev_GPU_DMA40_3 * 28 ; BCM2838
iDev_GPU_AuxInt * 29 ; shared SPI1, SPI2, UART1
iDev_GPU_ARM * 30 ; not on list in datasheet
......
......@@ -41,6 +41,16 @@ DMACB_STRIDE # 4
DMACB_NEXTCONBK # 4
DMACB_RESERVED # 8
^ 0
DMA4CB_TI # 4
DMA4CB_SRC # 4
DMA4CB_SRCI # 4
DMA4CB_DEST # 4
DMA4CB_DESTI # 4
DMA4CB_LEN # 4
DMA4CB_NEXT_CB # 4
DMA4CB_RESERVED # 4
DMACB_SIZE * @
DMACB_ALIGN * 32
......@@ -57,6 +67,20 @@ DMACH_STRIDE # 4 ; RO
DMACH_NEXTCONBK # 4 ; RO (RW when paused)
DMACH_DEBUG # 4 ; RW
^ 0
DMA4CH_CS # 4 ; RW
DMA4CH_CB # 4 ; RW
# 4
DMA4CH_DEBUG # 4 ; RW
DMA4CH_TI # 4 ; RO
DMA4CH_SRC # 4 ; RO
DMA4CH_SRCI # 4 ; RO
DMA4CH_DEST # 4 ; RO
DMA4CH_DESTI # 4 ; RO
DMA4CH_LEN # 4 ; RO
DMA4CH_NEXT_CB # 4 ; RO (RW when paused)
DMA4CH_DEBUG2 # 4 ; RO
; Stride of 256 bytes between each channel
DMA_CH_STRIDE * &100
......@@ -121,7 +145,92 @@ DMA_DEBUG_READ_ERROR * 1<<2
DMA_DEBUG_FIFO_ERROR * 1<<1
DMA_DEBUG_READ_LAST_NOT_SET_ERROR * 1<<0
; Peripheral DREQ values
; DMA4 register/CB bits
DMA4_CS_HALT * 1<<31
DMA4_CS_ABORT * 1<<30
DMA4_CS_DISDEBUG * 1<<29
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES * 1<<28
DMA4_CS_OUTSTANDING_TRANSACTIONS * 1<<25
DMA4_CS_DMA_BUSY * 1<<24
DMA4_CS_PANIC_QOS_SHIFT * 20
DMA4_CS_PANIC_QOS_MASK * &F
DMA4_CS_QOS_SHIFT * 16
DMA4_CS_QOS_MASK * &F
DMA4_CS_ERROR * 1<<10
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES * 1<<7
DMA4_CS_DREQ_STOPS_DMA * 1<<6
DMA4_CS_WR_PAUSED * 1<<5
DMA4_CS_RD_PAUSED * 1<<4
DMA4_CS_DREQ * 1<<3
DMA4_CS_INT * 1<<2
DMA4_CS_END * 1<<1
DMA4_CS_ACTIVE * 1<<0
DMA4_DEBUG_VERSION_SHIFT * 28
DMA4_DEBUG_VERSION_MASK * &F
DMA4_DEBUG_ID_SHIFT * 24
DMA4_DEBUG_ID_MASK * &F
DMA4_DEBUG_RESET * 1<<23
DMA4_DEBUG_W_STATE_SHIFT * 18
DMA4_DEBUG_W_STATE_MASK * &F
DMA4_DEBUG_R_STATE_SHIFT * 14
DMA4_DEBUG_R_STATE_MASK * &F
DMA4_DEBUG_DISABLE_CLK_GATE * 1<<11
DMA4_DEBUG_ABORT_ON_ERROR * 1<<10
DMA4_DEBUG_HALT_ON_ERROR * 1<<9
DMA4_DEBUG_INT_ON_ERROR * 1<<8
DMA4_DEBUG_READ_CB_ERROR * 1<<3
DMA4_DEBUG_READ_ERROR * 1<<2
DMA4_DEBUG_FIFO_ERROR * 1<<1
DMA4_DEBUG_WRITE_ERROR * 1<<0
DMA4_TI_D_WAITS_SHIFT * 24
DMA4_TI_D_WAITS_MASK * &FF
DMA4_TI_S_WAITS_SHIFT * 16
DMA4_TI_S_WAITS_MASK * &FF
DMA4_TI_D_DREQ * 1<<15
DMA4_TI_S_DREQ * 1<<14
DMA4_TI_PERMAP_SHIFT * 9
DMA4_TI_PERMAP_MASK * &1F
DMA4_TI_WAIT_RD_RESP * 1<<3
DMA4_TI_WAIT_RESP * 1<<2
DMA4_TI_TDMODE * 1<<1
DMA4_TI_INTEN * 1<<0
DMA4_SRCI_STRIDE_SHIFT * 16
DMA4_SRCI_STRIDE_MASK * &FFFF
DMA4_SRCI_IGNORE * 1<<15
DMA4_SRCI_SIZE_SHIFT * 13
DMA4_SRCI_SIZE_MASK * 3
DMA4_SRCI_INC * 1<<12
DMA4_SRCI_BURST_LENGTH_SHIFT * 8
DMA4_SRCI_BURST_LENGTH_MASK * &F
DMA4_SRCI_ADDR_SHIFT * 0
DMA4_SRCI_ADDR_MASK * &FF
DMA4_DESTI_STRIDE_SHIFT * 16
DMA4_DESTI_STRIDE_MASK * &FFFF
DMA4_DESTI_IGNORE * 1<<15
DMA4_DESTI_SIZE_SHIFT * 13
DMA4_DESTI_SIZE_MASK * 3
DMA4_DESTI_INC * 1<<12
DMA4_DESTI_BURST_LENGTH_SHIFT * 8
DMA4_DESTI_BURST_LENGTH_MASK * &F
DMA4_DESTI_ADDR_SHIFT * 0
DMA4_DESTI_ADDR_MASK * &FF
DMA4_LEN_YLENGTH_SHIFT * 16
DMA4_LEN_YLENGTH_MASK * &3FFF
DMA4_LEN_XLENGTH_SHIFT * 0
DMA4_LEN_XLENGTH_MASK * &FFFF
DMA4_DEBUG2_OUTSTANDING_READS_SHIFT * 16
DMA4_DEBUG2_OUTSTANDING_READS_MASK * &1FF
DMA4_DEBUG2_OUTSTANDING_WRITES_SHIFT * 0
DMA4_DEBUG2_OUTSTANDING_WRITES_MASK * &1FF
; Peripheral DREQ values (BCM2835-2837)
DREQ_NONE * 0
DREQ_DSI1 * 1
DREQ_PCM_TX * 2
......@@ -154,7 +263,43 @@ DREQ_SLIMBUS_DC7 * 29
DREQ_SLIMBUS_DC8 * 30
DREQ_SLIMBUS_DC9 * 31
; Peripheral DREQ values (BCM2838)
DREQ8_NONE * 0
DREQ8_DSI0__PWM1 * 1
DREQ8_PCM_TX * 2
DREQ8_PCM_RX * 3
DREQ8_SMI * 4
DREQ8_PWM0 * 5
DREQ8_SPI0_TX * 6
DREQ8_SPI0_RX * 7
DREQ8_BSC_SPI_SLAVE_TX * 8
DREQ8_BSC_SPI_SLAVE_RX * 9
DREQ8_HDMI0 * 10
DREQ8_EMMC * 11
DREQ8_UART0_TX * 12
DREQ8_SDHOST * 13
DREQ8_UART0_RX * 14
DREQ8_DSI1 * 15
DREQ8_SPI1_TX * 16
DREQ8_HDMI1 * 17
DREQ8_SPI1_RX * 18
DREQ8_UART3_TX__SPI4_TX * 19
DREQ8_UART3_RX__SPI4_RX * 20
DREQ8_UART5_TX__SPI5_TX * 21
DREQ8_UART5_RX__SPI5_RX * 22
DREQ8_SPI6_TX * 23
DREQ8_SCALER_FIFO_0_SMI * 24
DREQ8_SCALER_FIFO_1_SMI * 25
DREQ8_SCALER_FIFO_2_SMI * 26
DREQ8_SPI6_RX * 27
DREQ8_UART2_TX * 28
DREQ8_UART2_RX * 29
DREQ8_UART4_TX * 30
DREQ8_UART4_RX * 31
; Channels 7-14 are lite channels
DMA_CH_is_lite * &7F80
; BCM2838 channels 7-10 are lite channels
DMA_CH_is_lite_2838 * &0780
END
......@@ -56,7 +56,7 @@ DMACDREQ # 4 ; Peripheral/DREQ this channel is servicing
DMACOptions # 4 ; Options set by SetOptions
DMACPeriAddress # 4 ; VC phys addr of peripheral - i.e. at &7e......
DMACLastProgress # 4 ; Last progress value
DMACLastCONBLK_AD # 4 ; Last control block seen executing
DMACLastCONBLK_AD # 4 ; Last control block seen executing (phys addr, >>5 for DMA4)
DMACLastTXFR_LEN # 4 ; Last transfer length remaining seen
DMACCBOffset # 4 ; Address offset to convert DMA CB addr to ARM CB addr
DMACDesc # 32 ; Buffer for description string
......
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