Commit bfd45048 authored by John Ballance's avatar John Ballance
Browse files

Boots with May17th start.elf

Detail:
   Recent changes in the broadcom startup code now accomodated. frame buffer
   will now determine whether it is L2 cached or not, and be set up accordingly.
   ATAGs not currently read, so ram size defaulted.
  ** note that there will be further updates to this over the following days
  ** trackikng startup code changes.
   added HAL_TimerIRQClear entry
Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.03. Tagged as 'BCM2835-0_03'
parent 71e5f9c7
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.02"
Module_Version SETA 2
Module_MajorVersion SETS "0.03"
Module_Version SETA 3
Module_MinorVersion SETS ""
Module_Date SETS "20 May 2012"
Module_ApplicationDate SETS "20-May-12"
Module_Date SETS "23 May 2012"
Module_ApplicationDate SETS "23-May-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.02"
Module_HelpVersion SETS "0.02 (20 May 2012)"
Module_FullVersion SETS "0.03"
Module_HelpVersion SETS "0.03 (23 May 2012)"
END
/* (0.02)
/* (0.03)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.02
#define Module_MajorVersion_CMHG 0.03
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 May 2012
#define Module_Date_CMHG 23 May 2012
#define Module_MajorVersion "0.02"
#define Module_Version 2
#define Module_MajorVersion "0.03"
#define Module_Version 3
#define Module_MinorVersion ""
#define Module_Date "20 May 2012"
#define Module_Date "23 May 2012"
#define Module_ApplicationDate "20-May-12"
#define Module_ApplicationDate "23-May-12"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.02"
#define Module_HelpVersion "0.02 (20 May 2012)"
#define Module_LibraryVersionInfo "0:2"
#define Module_FullVersion "0.03"
#define Module_HelpVersion "0.03 (23 May 2012)"
#define Module_LibraryVersionInfo "0:3"
......@@ -92,6 +92,11 @@ IO_Size * &01000000
RAM_Base * &00000000 ; try off bottom
Boot_RAM_Base * &00000000
DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes
GPU_UnCached * &c0000000 ; GPU mempry mapping uncached
GPU_L2Conly * &80000000 ; GPU L2 Cached (only)
GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coherent
GPU_L1L2Cac * &00000000 ; both L1 and L2 cached GPU side
GPU_CacheMask * &c0000000
[ UseALBlob
; FB_MemBase is the point at which riscos is 'capped'
......@@ -218,7 +223,16 @@ MB_Chan_Btn * 5 ; Buttons channel
MB_Chan_TSc * 6 ; TouchScreen channel
; far end replies on the same channel when command done.. e.g.
; command c0000001 gets 00000001 (ie channel1) reply
; Power channel bits
MB_Pwr_SDCard * 0
MB_Pwr_UART * 1
MB_Pwr_MiniUART * 2
MB_Pwr_USB * 3
MB_Pwr_I2C0 * 4
MB_Pwr_I2C1_MASK * 5
MB_Pwr_I2C2_MASK * 6
MB_Pwr_SPI_MASK * 7
MB_Pwr_CCP2TX_MASK * 8
; mem barrier operation; ensures all explicit mem operations completed before
......@@ -226,25 +240,25 @@ MB_Chan_TSc * 6 ; TouchScreen channel
; (value 4 is all insructions, value 5 is just mem instructions)
; zeroes $r
MACRO
$label DataSyncBarrier $r
$label MOV $r, #0
MCR p15, 0, $r, c7, c10,4
$label DataSyncBarrier $r, $cond
$label MOV$cond $r, #0
MCR$cond p15, 0, $r, c7, c10,4
MEND
MACRO
$label DoMemBarrier $r
$label MOV $r, #0
MCR p15, 0, $r, c7, c10,5
$label DoMemBarrier $r, $cond
$label MOV$cond $r, #0
MCR$cond p15, 0, $r, c7, c10,5
MEND
MACRO
$label FlushDataCache $r
$label MOV $r, #0
MCR p15, 0, $r, c7, c6,0
$label FlushDataCache $r, $cond
$label MOV$cond $r, #0
MCR$cond p15, 0, $r, c7, c6,0
MEND
MACRO
$label FlushDataCacheRange $startaddr,$endaddr
$label BIC $startaddr, $startaddr, #&1f
BIC $endaddr, $endaddr, #&1f
MCRR p15, 0, $endaddr, $startaddr, c14
$label FlushDataCacheRange $startaddr,$endaddr,$cond
$label BIC$cond $startaddr, $startaddr, #&1f
BIC$cond $endaddr, $endaddr, #&1f
MCRR$cond p15, 0, $endaddr, $startaddr, c14
MEND
; GPIO register set
GPIO_Base * &00200000 ; base offset of GPIO regs
......
......@@ -48,6 +48,7 @@ DMAcb # sizeof_DMAcb
FB_Base # 4
FB_Size # 4
FB_CacheMode # 4
; align to 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
mbram # 0 ; structure needed for frame buffer descriptor
......
......@@ -66,6 +66,7 @@
EXPORT HAL_TimerSetPeriod
EXPORT HAL_TimerPeriod
EXPORT HAL_TimerReadCountdown
EXPORT HAL_TimerIRQClear
EXPORT HAL_CounterRate
EXPORT HAL_CounterPeriod
......@@ -161,23 +162,9 @@ HAL_IRQDisable
MOV R0,#1
MOV PC,R14
; used only to clear any IRQs latched in the irq controller itself
HAL_IRQClear
DataSyncBarrier a2 ; resync before writing peripheral
teq a1, #iDev_ARM_Timer ; timer device
ldreq a2, ARM_Timer_IO_Address
moveq a1, #1 ; timer device irq bit
streq a1, [a2,#12] ; clear the timer irq
moveq pc,lr
; code below needs to catch other devices
MOV R2, R0, LSR #32 ; which register?
MOV R2, R2, LSL #2 ; word offset
LDR R1,IRQ_Base_Address
AND R0, R0, #&1f ; isolate to within register
MOV R3,#1
MOV R3,R3,LSL R0
STR R3,[R1,R2]
DataSyncBarrier r3 ; resync before writing peripheral
MOV PC,R14
mov pc, lr
; This (inefficiently) assumes a device num to each of the 96 possible IRQ bits
HAL_IRQSource
......@@ -292,6 +279,14 @@ HAL_TimerReadCountdown
DataSyncBarrier a2 ; resync after reading peripheral
MOV pc,lr
; a0 is timer to clear =0 for system timer
HAL_TimerIRQClear
DataSyncBarrier a2 ; resync before writing peripheral
ldr a2, ARM_Timer_IO_Address
mov a1, #1 ; timer device irq bit
str a1, [a2,#12] ; clear the timer irq
mov pc,lr
HAL_CounterRate
; HALStub "HAL_CounterRate"
LDR a1,=1000000
......
......@@ -65,6 +65,7 @@
IMPORT HAL_TimerSetPeriod
IMPORT HAL_TimerPeriod
IMPORT HAL_TimerReadCountdown
IMPORT HAL_TimerIRQClear
IMPORT HAL_CounterRate
IMPORT HAL_CounterPeriod
......@@ -296,7 +297,7 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
]
LDR R4,mbox_addr
[ UseALBlob
MOV R5,#&80 + MB_Chan_Pwr
MOV R5,#&80 + MB_Chan_Pwr ; (looks like turn on USB)
STR R5,[R4,#MB_ChWr]
; For now, just assume that we have 40MB of memory...
......@@ -321,8 +322,8 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
]
str r1, mbbpp
ADR r1, mbram
ORR R3, R1, #DMA_RAM_Base + MB_Chan_FB
str r3, [r4, #MB_ChWr]
ORR R3, R1, #GPU_L2CnonAl + MB_Chan_FB; try with L2 cache on
10 str r3, [r4, #MB_ChWr]
11 ldr r0, [r4, #MB_Sta] ; await response
tst r0, #MB_Sta_Empty
bne %bt11
......@@ -334,7 +335,13 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
mov r0,r1
bl HAL_DebugHexTX4
ldr r1, mbbase
bic r1, r1, #DMA_RAM_Base
and r0, r1, #GPU_CacheMask
str r0, FB_CacheMode
bl HAL_DebugHexTX4
teq r1, #0 ;did we get an answer
ORREQ R3, R3, #GPU_UnCached + MB_Chan_FB; try with L2 cache off
BEQ %BT10 ; 0 size.. try with L2 off
bic r1, r1, #GPU_CacheMask
str r1, FB_Base
mov r0,r1
bl HAL_DebugHexTX4
......@@ -345,7 +352,7 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
[ HALDebug
[ SCR32
LDR R0,=1920*8*4
STR R1,ScreenBase
STR R1,ScreenBase ; for HAL use, remember address we were given
STR R0,BytesPerRow
MOV R0,#8*4
STR R0,BytesPerChar
......@@ -405,7 +412,7 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
ALIGN
]
]
[ {FALSE} ; nolonger used
; Traverse list of 'atags' structures
; word 0 = size of tag, including header, in words
; word 1 = type tag
......@@ -483,11 +490,74 @@ atag_next
TEQ a1,#ATAG_NONE
ADDNE v3, v3, a2, LSL #2
BNE atags_loop
|
ROMTOP * 6 <<20
RAMTOP * 128 <<20
; debug hack to force 128meg ram and 6meg rom
MOV v2, #ROMTOP ;start of available RAM, after HAL + OS image
MOV a1, #RAMTOP ; end of RAM
MOV a2, #0
MOV a3, #0
MOV a4, #0
MOV v4, #0
MOV v5, #0
MOV v7, #0
MOV ip, #0
MOV lr, #0
clear_lp1
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
CMP a1, v2
BHI clear_lp1
mov a2, v2
ADD a3, a2, #RAMTOP ; end of RAM
SUB a3, a3, #ROMTOP ; less what is used
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
MVN a4, #0
MOV a1, #0
STR a1, [sp, #-4]! ;reference handle (NULL for first call)
CallOSM OS_AddRAM
STR a1,[sp] ;ref for next call
]
[ HALDebug
ADR R0,start_os
BL output_text
]
[ {FALSE}
; fill the frame buffer
ldr v2, FB_Base
ldr a1, FB_Size
; debug hack to force 128meg ram and 6meg rom
LDR a2, =&00ffffff
ldr a3, =&ffffffff
ldr a4, =&00ffffff
ldr v4, =&ffffffff
ldr v5, =&00ffffff
ldr v7, =&ffffffff
ldr ip, =&00ffffff
ADD a1, v2, a1 ;end of RAM
MOV lr, #0
clear_lp12
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
CMP a1, v2
BHI clear_lp12
]
; OS kernel informed of RAM areas
LDR a4,[sp],#4 ;!!! ref from last AddRAM
......@@ -654,7 +724,7 @@ HAL_EntryTable DATA
HALEntry HAL_Video_IICOp
NullEntry ; HAL_TimerIRQClear
HALEntry HAL_TimerIRQClear
NullEntry ; HAL_TimerIRQStatus
HALEntry HAL_ExtMachineID
......@@ -673,21 +743,32 @@ HAL_Init
MOV R8,a2
BL SetUpOSEntries
MOV a4, sb ; confirm the caching mode in use in GPU
ADRL sb, workspace ; where we remembered it is
LDR a3, FB_Size
LDR a2, FB_Base ; effectively part of the ROM image
LDR a1, FB_CacheMode ; GPU cache mode
mov sb, a4
STR a3, FB_Size ; put in our workspace
STR a2, FB_Base ; for HAL_FramestoreAddress use
STR a1, FB_CacheMode
; Get the physical address of the start of our workspace
; R8 -> start of the page containing our workspace
MOV a1,R8
CallOS OS_LogToPhys
MOV a2,sb,LSL #20
ORR a1,a1,#DMA_RAM_Base
ORR a1,a1,a2,LSR #20 ; factor in start offset
STR a1,WSPhysAddr
MOV a1,#0 ; map in the IO space
LDR a2,=IO_Base
LDR a3,=IO_Size
MOV a2, sb, LSL #20
LDR a3, FB_CacheMode
ORR a1, a1, a3;#DMA_RAM_Base
ORR a1, a1, a2, LSR #20 ; factor in start offset
STR a1, WSPhysAddr
MOV a1, #0 ; map in the IO space
LDR a2, =IO_Base
LDR a3, =IO_Size
CallOS OS_MapInIO
STR a1,PeriBase
STR a1, PeriBase
BL Interrupt_Init ; initialise our interrupts
BL Timer_Init
......@@ -697,20 +778,17 @@ HAL_Init
; Map in the frame buffer
; and initialise the display driver
MOV a4, sb
ADRL sb, workspace ; where we remembered it is
LDR a3, FB_Size
LDR a2, FB_Base ; effectively part of the ROM image
mov sb, a4
STR a3, FB_Size ; put in our workspace
STR a2, FB_Base ; for HAL_FramestoreAddress use
; LDR a1, FB_CacheMode
; ORR a2, a2, a1 ; combine in the address we need 'the other side'
mov r0,a2
bl HAL_DebugHexTX4
mov r0,a3
bl HAL_DebugHexTX4
MOV a1,#0
STR a1,LastInt
STR a1,CurAddr
MOV a1, #0
STR a1, LastInt
STR a1, CurAddr
CallOS OS_MapInIO
STR a1,ScreenBase
......
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