Commit afc8ef8d authored by Robert Sprowson's avatar Robert Sprowson

Move CMOS settings out of riscos.img

The Pi is unusual in self modifying the ROM image when a CMOS setting was changed (due to there being none on the PCB), with the potential of ending up with a corrupt OS image on disc.
Remove this code and emulate the CMOS using normal RAM, and using the Pi firmware to load the CMOS file in for us (like fatload does on OMAP based designs) by using its ability to load a second arbitrary file at an address, intended in the Linux world to load a disc image.

To use this you will need to add
  ramfsfile=CMOS
  ramfsaddr=0x508000
to config.txt which loads it 5MB (ie. ImageSize) above the default load address (&8000), though as noted in the changes to BCM2835-0_60 we don't really need to load at offset &8000 but generally do since that's the Pi firmware's default.

hdr/StaticWS:
New workspace to hold our CMOS copy.
CMOS.s:
Remove the 2k magic block, add a simple bytewise copy loop implementation.
SDIO.s:
Extend ADR range.
Top.s:
Copy what the Pi firmware loads somewhere safe until the MMU is on, then copy it back (converting from logical to physical order along the way).
Change other values recovered from pre-MMU times using advanced post indexed addressing technology (TM) rather than switching around sb a lot.

Tested on a Pi 3, with and without an initial CMOS file present.

Version 0.61. Tagged as 'BCM2835-0_61'
parent 9192c127
/* (0.60)
/* (0.61)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.60
#define Module_MajorVersion_CMHG 0.61
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 15 Oct 2016
#define Module_MajorVersion "0.60"
#define Module_Version 60
#define Module_MajorVersion "0.61"
#define Module_Version 61
#define Module_MinorVersion ""
#define Module_Date "15 Oct 2016"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.60"
#define Module_HelpVersion "0.60 (15 Oct 2016)"
#define Module_LibraryVersionInfo "0:60"
#define Module_FullVersion "0.61"
#define Module_HelpVersion "0.61 (15 Oct 2016)"
#define Module_LibraryVersionInfo "0:61"
......@@ -135,6 +135,8 @@ NCNBPhysAddr # 4 ;VC physical address of NCNB workspace
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
SimulatedCMOS # 2048+4 ;Usual 2k plus version word (as appended by *SaveCMOS)
SDHCIWriteInterval # 4 ; minimum counter ticks between writes
SDHCILastWriteCount # 4 ; counter value at last write
SDHCIInputClock # 4 ; estimated speed of input clock to SDHCI block
......
......@@ -32,7 +32,9 @@
AREA |ARM$$data|, CODE, READONLY, PIC
GET Hdr:ListOpts
GET Hdr:HALEntries
GET hdr.StaticWS
EXPORT HAL_NVMemoryType
EXPORT HAL_NVMemorySize
......@@ -42,27 +44,17 @@
EXPORT HAL_NVMemoryRead
EXPORT HAL_NVMemoryWrite
cmos_size * 2048 ; arbitrary choice
UND #&C305 ; get it?
DCD cmos_size
cmos
% cmos_size
cmos_stamp
DCB 0, 0, 0, 0, 0 ; space for a UTC save time
ALIGN
HAL_NVMemoryType
; HAL provides calls to access NVMemory, physical locations 0-15 are read/write
LDR a1, =NVMemoryFlag_HAL :OR: NVMemoryFlag_LowRead :OR: NVMemoryFlag_LowWrite
MOV pc,lr
HAL_NVMemorySize
MOV a1,#cmos_size
MOV a1,#?SimulatedCMOS - 4 ; Less the version word
MOV pc,lr
HAL_NVMemoryPageSize
MOV a1,#cmos_size
MOV a1,#16 ; Simulation doesn't really have a concept of pages
MOV pc,lr
HAL_NVMemoryProtectedSize
......@@ -72,18 +64,32 @@ HAL_NVMemoryProtectedSize
HAL_NVMemoryProtection
MOV pc,lr
HAL_NVMemoryRead
ADRL ip,cmos
HAL_NVMemoryRead ROUT
; a1 = physical address
; a2 = buffer
; a3 = number of bytes requested
; Returns a1 = number of bytes read
ADR ip,SimulatedCMOS
ADD ip,ip,a1
MOVS a1,a3
nvr_lp LDRNEB a4,[ip],#1
10 LDRNEB a4,[ip],#1
STRNEB a4,[a2],#1
SUBNES a3,a3,#1
BNE nvr_lp
BNE %BT10
MOV pc,lr
HAL_NVMemoryWrite
MOV a1,a3
HAL_NVMemoryWrite ROUT
; a1 = physical address
; a2 = buffer
; a3 = number of bytes to do
; Returns a1 = number of bytes written
ADR ip,SimulatedCMOS
ADD ip,ip,a1
MOVS a1,a3
10 LDRNEB a4,[a2],#1
STRNEB a4,[ip],#1
SUBNES a3,a3,#1
BNE %BT10
MOV pc,lr
END
......@@ -380,7 +380,7 @@ SDIO_InitDevices ROUT
STR a1, SDHCISlotInfo + HALDeviceSDHCI_SlotInfo_StdRegs
; SlotInfo
ADR a1, SDHCISlotInfo
ADRL a1, SDHCISlotInfo
STR a1, SDHCIDevice + HALDevice_SDHCISlotInfo
; SlotInfo_Flags
......
......@@ -150,7 +150,7 @@
EXPORT HAL_Base
IMPORT RamAd
IMPORT SerNo
IMPORT memcpy
[ HALDebug
EXPORT HAL_DebugHexTX4
......@@ -264,6 +264,15 @@ start
LDR r0,=(16:SHL:MB_Pwr_USB)+MB_Chan_Pwr
BL HAL_SendHostMessage
; From config.txt we might have loaded some CMOS settings above the ROM,
; import those into our workspace (they may subsequently turn out to be junk)
ADRL a1, HAL_Base + OSROM_HALSize
LDR a3, [a1, #OSHdr_ImageSize]
ADD a2, a3, a1 ; loaded immediately after OS image
ADR a1, SimulatedCMOS
LDR a3, =?SimulatedCMOS
BL memcpy
; Query the platform and set up a frame buffer.
BL HAL_QueryPlatform
......@@ -671,41 +680,37 @@ HAL_Init
]
]
MOV a4, sb ; confirm the caching mode in use in GPU
ADRL sb, workspace ; where we remembered it is
LDR a1, FB_CacheMode ; GPU cache mode
LDR a2, TouchBuf
LDR a3, VirtGPIOBuf
mov sb, a4
STR a1, FB_CacheMode
; Recover various values that are now trapped in ROM from when the workspace
; and ROM overlapped prior to relocation. Copy them into RW memory at sb.
ADRL a4, workspace ; where they are post ROM relocation
LDR a1, [a4, #:INDEX:FB_CacheMode]
LDR a2, [a4, #:INDEX:TouchBuf]
LDR a3, [a4, #:INDEX:VirtGPIOBuf]
STR a1, FB_CacheMode ; GPU cache mode
STR a2, TouchBuf
STR a3, VirtGPIOBuf
ADRL sb, workspace ; where we remembered it is
LDR a3, VC_Size
LDR a2, VC_Base
LDR a1, ARM_Base
LDR ip, ARM_Size
mov sb, a4
LDR a3, [a4, #:INDEX:VC_Size]
LDR a2, [a4, #:INDEX:VC_Base]
LDR a1, [a4, #:INDEX:ARM_Base]
LDR ip, [a4, #:INDEX:ARM_Size]
STR a3, VC_Size
STR a2, VC_Base
STR a1, ARM_Base
STR ip, ARM_Size
ADRL sb, workspace ; where we remembered it is
LDR a3, Board_Model
LDR a2, Board_Revision
LDR a1, ARM_DMAChannels
mov sb, a4
LDR a3, [a4, #:INDEX:Board_Model]
LDR a2, [a4, #:INDEX:Board_Revision]
LDR a1, [a4, #:INDEX:ARM_DMAChannels]
STR a3, Board_Model
STR a2, Board_Revision
STR a1, ARM_DMAChannels
LDR a2, VC_Base
LDR a3, VC_Size
[ HALDebug
MOV a1, a2
LDR a1, VC_Base
BL HAL_DebugHexTX4
MOV a1, a3
LDR a1, VC_Size
BL HAL_DebugHexTX4
]
......@@ -729,7 +734,7 @@ HAL_Init
CallOS OS_MapInIO
STR a1, VirtGPIOBuf
10
BL CMOS_Init
BL Interrupt_Init ; initialise our interrupts
BL Timer_Init
BL IIC_Init
......@@ -742,6 +747,45 @@ HAL_Init
Pull "v5, pc"
; Initialise the simulated CMOS.
CMOS_Init ROUT
Push "v1, lr"
ADRL a1, workspace ; where it got relocated to
ADD v1, a1, #:INDEX:SimulatedCMOS
LDR a4, [v1, #?SimulatedCMOS - 4]
SUB a4, a4, #500 ; Check version word is from RISC OS 5
CMP a4, #100
BHS %FT10
; Now we need to take the logical CMOS file order and make it physical
; The resulting layout from logical is [F0-FF][C0-EF][00-BF][100-END]
ADR a1, SimulatedCMOS
ADD a2, v1, #&F0
MOV a3, #16*1
BL memcpy
ADD a1, a1, #16*1
ADD a2, v1, #&C0
MOV a3, #16*3
BL memcpy
ADD a1, a1, #16*3
ADD a2, v1, #0
MOV a3, #16*12
BL memcpy
ADD a1, a1, #16*12
ADD a2, v1, #&100
MOV a3, #?SimulatedCMOS - 4 - &100
BL memcpy
Pull "v1, pc"
10
ADR a1, SimulatedCMOS
MOV a2, #-1 ; Zap it to a known blank state
LDR a3, =?SimulatedCMOS - 4
20
STR a2, [a1, a3]
SUBS a3, a3, #4
BPL %BT20
Pull "v1, pc"
; Initialise and relocate the entry table.
SetUpOSEntries ROUT
STR a1, OSheader
......
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