Commit af7cf4e9 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add support code required for DWCDriver 'FIQ fix'

Detail:
  hdr/BCM2835, hdr/USB, s/USB - Update HAL_USBControllerInfo to return the MPHI address & IRQ number
  s/Interrupts - Add some missing memory barriers. Change FIQ enable/disable calls to not alter IRQ masking of the interrupt - simplifies the code and avoids any ordering issues with code that switches interrupts between IRQ & FIQ
  s/Timers - Add missing memory barrier
Admin:
  Tested on Raspberry Pi
  Requires Kernel-5_35-4_79_2_227 to build


Version 0.34. Tagged as 'BCM2835-0_34'
parent 7380897b
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.33"
Module_Version SETA 33
Module_MajorVersion SETS "0.34"
Module_Version SETA 34
Module_MinorVersion SETS ""
Module_Date SETS "29 Apr 2014"
Module_ApplicationDate SETS "29-Apr-14"
Module_Date SETS "19 Jun 2014"
Module_ApplicationDate SETS "19-Jun-14"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.33"
Module_HelpVersion SETS "0.33 (29 Apr 2014)"
Module_FullVersion SETS "0.34"
Module_HelpVersion SETS "0.34 (19 Jun 2014)"
END
/* (0.33)
/* (0.34)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.33
#define Module_MajorVersion_CMHG 0.34
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Apr 2014
#define Module_Date_CMHG 19 Jun 2014
#define Module_MajorVersion "0.33"
#define Module_Version 33
#define Module_MajorVersion "0.34"
#define Module_Version 34
#define Module_MinorVersion ""
#define Module_Date "29 Apr 2014"
#define Module_Date "19 Jun 2014"
#define Module_ApplicationDate "29-Apr-14"
#define Module_ApplicationDate "19-Jun-14"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.33"
#define Module_HelpVersion "0.33 (29 Apr 2014)"
#define Module_LibraryVersionInfo "0:33"
#define Module_FullVersion "0.34"
#define Module_HelpVersion "0.34 (19 Jun 2014)"
#define Module_LibraryVersionInfo "0:34"
......@@ -412,6 +412,9 @@ DMA_Base * &00007000
; DMA_CH_Count * 13 ; Allegedly 16 channels, but can only get IRQs from 13 of them?
DMA_CH_Count * 12 ; Was 13, but firmware bug is incorrectly reporting that ch 12 is available
; Message-based parallel host interface
MPHI_Base * &00006000
;
PM_Base * &00100000 ; power management
PM_Rstc * &1c ; reset control reg
......
......@@ -33,6 +33,8 @@ USBINFO_FLAGS # 4 ; See below
USBINFO_HW # 4 ; Base addr
USBINFO_DEVNO # 4 ; IRQ number
USBINFO_DMAOFFSET # 4 ; Offset to convert ARM phys addrs to DMA addrs
USBINFO_HW_MPHI # 4 ; MPHI address
USBINFO_DEVNO_MPHI # 4 ; MPHI IRQ number
USBINFO_SIZEOF # 0 ; Size of struct
USBINFO_FLAG_HAL_USBPortPower * 1 ; Use HAL_USBPortPower
......
......@@ -108,15 +108,16 @@ HAL_IRQSource
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_ARM_Timer ; 64
MOVPL pc, lr
BPL %FT90
LDR a1, [a2, #IRQ_PEND2]
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_GPU_HostPort ; 32
MOVPL pc, lr
BPL %FT90
LDR a1, [a2, #IRQ_PEND1]
CLZ a1, a1
RSB a1, a1, #31
90
DoMemBarrier ip
MOV pc, lr
......@@ -157,13 +158,6 @@ HAL_FIQEnable
TEQ a3, a4 ; Z set => FIQs already enabled
STR a4, [ip, #IRQ_FIQCTL]
ADD ip, ip, #IRQ_EN1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; enable our bit
MOVEQ a1, #1
MOVNE a1, #0
DoMemBarrier ip
......@@ -176,18 +170,11 @@ HAL_FIQDisable
DoMemBarrier ip
LDR ip, IRQ_Base_Address
ADD ip, ip, #IRQ_DIS1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; disable our bit
LDRB a3, [ip, #IRQ_FIQCTL-IRQ_DIS1] ; LDRB helpfully masks out bits 8-31 for us
LDRB a3, [ip, #IRQ_FIQCTL] ; LDRB helpfully masks out bits 8-31 for us
ORR a4, a1, #FIQEnable
TEQ a3, a4 ; Z set => FIQs already enabled
MOV a4, #0
STR a4, [ip, #IRQ_FIQCTL-IRQ_DIS1]
STR a4, [ip, #IRQ_FIQCTL]
MOVEQ a1, #1
MOVNE a1, #0
......@@ -202,15 +189,8 @@ HAL_FIQDisableAll
TST a1, #FIQEnable
MOVEQ pc, lr ; FIQs weren't enabled
AND a1, a1, #FIQSourceMask
ADD ip, ip, #IRQ_DIS1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; disable our bit
MOV a4, #0
STR a4, [ip, #IRQ_FIQCTL-IRQ_DIS1]
STR a4, [ip, #IRQ_FIQCTL]
DoMemBarrier ip
MOV pc, lr
......
......@@ -191,6 +191,7 @@ HAL_TimerReadCountdown ROUT
; Read failed
90 MOV a1, #0
DoMemBarrier ip
MOV pc, lr
......
......@@ -33,6 +33,7 @@
AREA |ARM$$code|, CODE, READONLY, PIC
GET Hdr:ListOpts
GET Hdr:HALEntries
GET hdr.BCM2835
GET hdr.StaticWS
GET hdr.USB
......@@ -52,20 +53,24 @@ HAL_USBControllerInfo
MOVHI a1, #0
MOVHI pc, lr
; Fill in the usbinfo struct
MOV a1, #3 ; DWC
MOV a1, #HALUSBControllerType_SynopsysDWC
STR a1, [a2, #USBINFO_TYPE]
CMP a3, #USBINFO_SIZEOF
MOV a1, #USBINFO_SIZEOF
MOVLO pc, lr
MOV a4, #0 ; flags
STR a4, [a2, #USBINFO_FLAGS]
LDR a4, PeriBase
ADD a4, a4, #USB_Base
LDR ip, PeriBase
ADD a4, ip, #USB_Base
STR a4, [a2, #USBINFO_HW]
MOV a4, #iDev_GPU_VCUSB
STR a4, [a2, #USBINFO_DEVNO]
LDR a4, FB_CacheMode
STR a4, [a2, #USBINFO_DMAOFFSET]
ADD a4, ip, #MPHI_Base
STR a4, [a2, #USBINFO_HW_MPHI]
MOV a4, #iDev_GPU_HostPort
STR a4, [a2, #USBINFO_DEVNO_MPHI]
MOV pc, lr
HAL_USBPortPower
......
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