Commit ae6f7f27 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

Add remaining PCIe setup steps

Memory window now enabled on the VIA VL805, on-chip bridge set to forward memory transactions, ARM CPU to PCI address space translated.
Since we know there's only the VIA chip on the bus, there's no dynamic probing going on like platforms that have PCI sockets. Its BAR settings are derived from defines at the top of PCI.s, so to browse the XHCI capability registers just peek at
  *Memory p 600100000 +20
Only 1 of the 4 address space translation windows is used.
parent 223182f1
......@@ -938,11 +938,41 @@ PCIe_MISC_CTRL * &4008
PCIe_MISC_CTRL_SCV_ACCESS_EN * 1:SHL:12
PCIe_MISC_CTRL_CFG_READ_SAFE * 1:SHL:13
PCIe_MISC_CTRL_MAX_BURST_SHIFT * 20
PCIe_PCI_MEM_LO_WIN0 * &400C
PCIe_PCI_MEM_HI_WIN0 * &4010
PCIe_PCI_MEM_LO_WIN1 * &4014
PCIe_PCI_MEM_HI_WIN1 * &4018
PCIe_PCI_MEM_LO_WIN2 * &401C
PCIe_PCI_MEM_HI_WIN2 * &4020
PCIe_PCI_MEM_LO_WIN3 * &4024
PCIe_PCI_MEM_HI_WIN3 * &4028
PCIe_RC_CONFIG_LO_BAR1 * &402C
PCIe_RC_CONFIG_HI_BAR1 * &4030
PCIe_RC_CONFIG_LO_BAR2 * &4034 ; For inbound memory
PCIe_RC_CONFIG_HI_BAR2 * &4038 ; transfers PCI->CPU
PCIe_RC_CONFIG_LO_BAR3 * &403C
PCIe_RC_CONFIG_HI_BAR3 * &4040
PCIe_LINK_STATUS * &4068
PCIe_LINK_STATUS_PORT * 1:SHL:7
PCIe_LINK_STATUS_IN_L23 * 1:SHL:6
PCIe_LINK_STATUS_DOWNLINK_ACT * 1:SHL:5
PCIe_LINK_STATUS_PHYLINK_UP * 1:SHL:4
PCIe_CPU_MEM_BASE_LIMIT_WIN0 * &4070
PCIe_CPU_MEM_BASE_LIMIT_WIN1 * &4074
PCIe_CPU_MEM_BASE_LIMIT_WIN2 * &4078
PCIe_CPU_MEM_BASE_LIMIT_WIN3 * &407C
PCIe_CPU_MEM_BASE_SHIFT * 4
PCIe_CPU_MEM_BASE_MASK * &FFF:SHL:PCIe_CPU_MEM_BASE_SHIFT
PCIe_CPU_MEM_LIMIT_SHIFT * 20
PCIe_CPU_MEM_LIMIT_MASK * &FFF:SHL:PCIe_CPU_MEM_LIMIT_SHIFT
PCIe_CPU_MEM_BASE_HI_WIN0 * &4080
PCIe_CPU_MEM_LIMIT_HI_WIN0 * &4084
PCIe_CPU_MEM_BASE_HI_WIN1 * &4088
PCIe_CPU_MEM_LIMIT_HI_WIN1 * &408C
PCIe_CPU_MEM_BASE_HI_WIN2 * &4090
PCIe_CPU_MEM_LIMIT_HI_WIN2 * &4094
PCIe_CPU_MEM_BASE_HI_WIN3 * &4098
PCIe_CPU_MEMLIMIT_HI_WIN3 * &409C
PCIe_INTR2_STATUS * &4300
PCIe_INTR2_SET * &4304
PCIe_INTR2_CLEAR * &4308
......
......@@ -55,6 +55,13 @@ PCILinkUpDelay * 1000 ; Microseconds
PCIResetDelay * 1000 ; Microseconds
; Config layout
PCIViaMemBase * &00100000 ; Non-zero, just so nobody thinks it's disabled
PCIWinMemBaseHi * 0
PCIWinMemBaseLo * &00000000 ; PCI view offset
CPUWinMemBaseHi * 6
CPUWinMemBaseLo * &00000000 ; CPU view offset
CPUWinMemSize * &08000000 ; Arbitrary, but at least big enough to encompass &00000000...PCIViaMemBase
PCI_Init ROUT
CPUDetect a1
MOVLS pc, lr
......@@ -120,19 +127,67 @@ PCI_Init ROUT
TEQEQ a1, #1 ; Bridge
Pull "v1-v3, pc",NE
; Ensure the VIA USB chip appears as bus 0/devfn 0
; Ensure the VIA USB chip appears as bus 1/devfn 0
MOV a1, #0
STRB a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_PrimaryBus]
MOV a1, #1
STRB a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_SecondaryBus]
STRB a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_SubordinateBus]
[ {FALSE}
; Pass memory transactions to the secondary
MOV a1, #PCICmd_BusMaster :OR: PCICmd_Memory
STRB a1, [v1, #PCIe_BRIDGE_CFG + PCIConf_Command]
; Set limit < base, no prefetchable memory
MOV a1, #&0010
STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_PrefetchableBase]
MOV a1, #&0000
STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_PrefetchableLimit]
; Set limit & base for memory transactions
MOV a1, #PCIWinMemBaseLo:SHR:16
STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_MemoryBase]
LDR a2, =CPUWinMemSize - 1 ; Inclusive limit
ADD a1, a2, #PCIWinMemBaseLo
MOV a1, a2, LSR #16
STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_MemoryLimit]
; Unlike platforms where there are sockets on the motherboard into which arbitrary
; PCI cards could be plugged, there are only known devices present, so there's no need
; to go probing and allocating memory space - just set up the BARs from hardcoded knowledge.
|
! 0, "PCIe not yet configuring memory/IO windows"
]
MOV a4, #PCIViaMemBase
MOV a3, #PCIConf0_BaseAddresses
MOV a2, #0
MOV a1, #0 ; VL805 is dev/bus/fn 0
BL HAL_PCIWriteConfigWord
MOV a4, #PCICmd_BusMaster :OR: PCICmd_Memory
MOV a3, #PCIConf_Command
MOV a2, #0
MOV a1, #0 ; VL805 is dev/bus/fn 0
BL HAL_PCIWriteConfigByte
; PCI side of outbound window
MOV a1, #PCIWinMemBaseLo
LDR a3, =PCIe_PCI_MEM_LO_WIN0
STR a1, [a3, v1]!
MOV a1, #PCIWinMemBaseHi
STR a1, [a3, #PCIe_PCI_MEM_HI_WIN0 - PCIe_PCI_MEM_LO_WIN0]
; CPU side of outbound window
MOV a1, #CPUWinMemBaseLo
MOV a2, #CPUWinMemBaseHi
STR a2, [a3, #PCIe_CPU_MEM_BASE_HI_WIN0 - PCIe_PCI_MEM_LO_WIN0]
LDR a4, =CPUWinMemSize - 1 ; Inclusive limit
ADDS a1, a1, a4
ADC a2, a2, #0
STR a2, [a3, #PCIe_CPU_MEM_LIMIT_HI_WIN0 - PCIe_PCI_MEM_LO_WIN0]
MOV a4, #CPUWinMemBaseLo:SHR:20 ; Now in MB
ASSERT PCIe_CPU_MEM_LIMIT_SHIFT = 20
BFC a1, #0, #20 ; Now in MB and promoted
ORR a1, a1, a4, LSL #PCIe_CPU_MEM_BASE_SHIFT
STR a1, [a3, #PCIe_CPU_MEM_BASE_LIMIT_WIN0 - PCIe_PCI_MEM_LO_WIN0]
Pull "v1-v3, pc"
HAL_PCIWriteConfigByte ROUT
......@@ -156,15 +211,8 @@ HAL_PCIReadConfigWord
CMP a1, #1 ; Range check the bus
CMPCC a2, #256 ; Range check the 5:3 devfn
MVNCS a1, #0
MOVCS pc, lr
[ {FALSE}
; Massage bus/devfn into index format
MOV a1, a1, LSL #PCIe_EXT_CFG_INDEX_BUS_SHIFT
ASSERT (PCIe_EXT_CFG_INDEX_DEV_SHIFT - PCIe_EXT_CFG_INDEX_FN_SHIFT) = 3
ASSERT (PCIe_EXT_CFG_INDEX_BUS_SHIFT - PCIe_EXT_CFG_INDEX_DEV_SHIFT) = 5
ASSERT PCIe_EXT_CFG_INDEX_DEV_SHIFT > PCIe_EXT_CFG_INDEX_FN_SHIFT
ORR a1, a1, a2, LSL #PCIe_EXT_CFG_INDEX_FN_SHIFT
MOVCS pc, lr
|
; Accessing non existant bus/devfn combinations stalls for a few seconds
ORRS a1, a1, a2
......@@ -173,7 +221,17 @@ HAL_PCIReadConfigWord
RSBNE ip, ip, #32
MOVNE a1, a1, LSR ip ; Clip to byte/halfword/word
MOVNE pc, lr
; So map bus 0/devfn 0 in RISC OS to bus 1/devfn 0 via the bridge
MOV a1, #1
]
; Massage bus/devfn into index format
MOV a1, a1, LSL #PCIe_EXT_CFG_INDEX_BUS_SHIFT
ASSERT (PCIe_EXT_CFG_INDEX_DEV_SHIFT - PCIe_EXT_CFG_INDEX_FN_SHIFT) = 3
ASSERT (PCIe_EXT_CFG_INDEX_BUS_SHIFT - PCIe_EXT_CFG_INDEX_DEV_SHIFT) = 5
ASSERT PCIe_EXT_CFG_INDEX_DEV_SHIFT > PCIe_EXT_CFG_INDEX_FN_SHIFT
ORR a1, a1, a2, LSL #PCIe_EXT_CFG_INDEX_FN_SHIFT
LDR a2, PeriBase2
ADD a2, a2, #PCIe_Base
ADD a2, a2, #PCIe_EXT_CFG_INDEX
......
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