From a86bcb4d5880aefdaa52ccd5832712b7d6526f52 Mon Sep 17 00:00:00 2001 From: Robert Sprowson Date: Sun, 23 Aug 2020 21:53:40 +0100 Subject: [PATCH] Remove double PCIe bridge mapping The bridge was incorrectly configured with 2 overlapping mappings (0-&FFFFFFFF and another 0-&8000000). When the VL805 wanted to bus master into main memory the bridge was confused where the transaction should go, causing a master abort to be logged on the secondary side. Reorganise the PCI memory so that only a small window in the top 1GB is actively decoded (we can't bus master above 3GB anyway due to a chip design "feature"), meaning the rest of the secondary address space is forwarded 1:1 to the primary. Further, because the CPU side windows can only be sized in powers of 2, reduce that to 2GB in size. --- s/PCI | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/s/PCI b/s/PCI index 07c357b..7032d9b 100644 --- a/s/PCI +++ b/s/PCI @@ -58,16 +58,24 @@ PCILinkUpTries * 1000 PCILinkUpDelay * 1000 ; Microseconds PCIResetDelay * 250 ; Microseconds -; Config layout -PCIViaMemBase * &00100000 ; Non-zero, just so nobody thinks it's disabled +; Memory layout +; ARM view PCI view +; OB Cfg 00FD500000-00FD500100 Root complex's virtual bridge +; 00FD508000-00FD508100 VL805 assuming PCIe_EXT_CFG_INDEX has selected it +; OB IO Disabled Unused +; OB Memory 06C0000000-06C00FFFFF 00C0000000-00C00FFFFF +; IB Memory 0000000000-007FFFFFFF 0000000000-007FFFFFFF +; +PCIViaMemBase * &C0000000 ; Up above 3GB +PCIViaMemSize * &00800000 ; Arbitrary, there aren't that many registers PCIWinMemBaseHi * 0 PCIWinMemBaseLo * &00000000 ; PCI view offset CPUWinMemBaseHi * 6 CPUWinMemBaseLo * &00000000 ; CPU view offset -CPUWinMemSize * &08000000 ; Arbitrary, but at least big enough to encompass &00000000...PCIViaMemBase +CPUWinMemSize * PCIViaMemBase + PCIViaMemSize PCIIBOffsetHi * 0 PCIIBOffsetLo * &00000000 ; PCI inbound offset to CPU physical address -PCIIBSizeLog2 * 32 +PCIIBSizeLog2 * 31 PCI_Init ROUT CPUDetect a1 @@ -173,11 +181,10 @@ PCI_Init ROUT STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_PrefetchableLimit] ; Set limit & base for memory transactions - MOV a1, #PCIWinMemBaseLo:SHR:16 + MOV a1, #(PCIWinMemBaseLo + PCIViaMemBase):SHR:16 + ASSERT PCIWinMemBaseHi = 0 ; Bridge is in 32 bit mode STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_MemoryBase] - LDR a2, =CPUWinMemSize - 1 ; Inclusive limit - ADD a1, a2, #PCIWinMemBaseLo - MOV a1, a2, LSR #16 + LDR a1, =(PCIWinMemBaseLo + PCIViaMemBase + PCIViaMemSize - 1):SHR:16 STRH a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_MemoryLimit] ; Unlike platforms where there are sockets on the motherboard into which arbitrary @@ -218,7 +225,7 @@ PCI_Init ROUT MOV a1, #CPUWinMemBaseLo MOV a2, #CPUWinMemBaseHi STR a2, [a3, #PCIe_CPU_MEM_BASE_HI_WIN0 - PCIe_PCI_MEM_LO_WIN0] - LDR a4, =CPUWinMemSize - 1 ; Inclusive limit + LDR a4, =CPUWinMemSize - 1 ; Inclusive limit ADDS a1, a1, a4 ADC a2, a2, #0 STR a2, [a3, #PCIe_CPU_MEM_LIMIT_HI_WIN0 - PCIe_PCI_MEM_LO_WIN0] -- GitLab