Commit a1c4df2f authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Use BCS1 instead of BCS0 for IIC when running on rev 2 boards

Detail:
  hdr/BCM2835, hdr/StaticWS, s/IIC - On rev 2 boards the usage of BSC0 and BSC1 have been swapped, such that BSC1 is now sent to the expansion header instead of BSC0.
  To allow RISC OS to continue to work with clock chips and other hardware fitted to the header, expose BSC1 to RISC OS if on a rev 2 board, or BSC0 if on a rev 1.
Admin:
  Changes received from Dave Higton
  Tested by Dave on rev 1 & rev 2 boards, with IIC devices
  Tested by me on rev 1 board (with no IIC devices fitted)


Version 0.24. Tagged as 'BCM2835-0_24'
parent 5a8b82be
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.23"
Module_Version SETA 23
Module_MajorVersion SETS "0.24"
Module_Version SETA 24
Module_MinorVersion SETS ""
Module_Date SETS "09 Sep 2012"
Module_ApplicationDate SETS "09-Sep-12"
Module_Date SETS "10 Sep 2012"
Module_ApplicationDate SETS "10-Sep-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.23"
Module_HelpVersion SETS "0.23 (09 Sep 2012)"
Module_FullVersion SETS "0.24"
Module_HelpVersion SETS "0.24 (10 Sep 2012)"
END
/* (0.23)
/* (0.24)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.23
#define Module_MajorVersion_CMHG 0.24
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 09 Sep 2012
#define Module_Date_CMHG 10 Sep 2012
#define Module_MajorVersion "0.23"
#define Module_Version 23
#define Module_MajorVersion "0.24"
#define Module_Version 24
#define Module_MinorVersion ""
#define Module_Date "09 Sep 2012"
#define Module_Date "10 Sep 2012"
#define Module_ApplicationDate "09-Sep-12"
#define Module_ApplicationDate "10-Sep-12"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.23"
#define Module_HelpVersion "0.23 (09 Sep 2012)"
#define Module_LibraryVersionInfo "0:23"
#define Module_FullVersion "0.24"
#define Module_HelpVersion "0.24 (10 Sep 2012)"
#define Module_LibraryVersionInfo "0:24"
......@@ -545,7 +545,9 @@ iDev_ARM_Uart * 64+19 ; copy of GPU IRQ 57
iDev_ARM_VCSDIO * 64+20 ; copy of GPU IRQ 62
;IIC0 (BSC0, i.e. Broadcom Serial Controller 0)
IIC_Base * &00205000 ; base of IIC0
IIC_Base0 * &00205000 ; base of IIC0
;IIC1 (BCS1, i.e. Broadcom Serial Controller 1)
IIC_Base1 * &00804000
IIC_C * &00 ; Control
IIC_S * &04 ; Status
IIC_DLEN * &08 ; Data Length
......
......@@ -85,6 +85,17 @@ MMUOffBaseAddr # 4 ; original address kernel was loade
MachineID # 8 ; derived from MAC address if there
IIC_Status # 4 ; Non-zero if an IIC transfer is going on
; NOTE - The following locations are for the base addresses of the
; controllers that RISC OS uses for bus 0 and bus 1. The use is
; dependent on board revision. Revision 1 boards (Board_Revision
; values 0..3) use Broadcom controller 0 for RISC OS bus 0 and
; Broadcom 1 for RISC OS 1. Revision 2 boards (Board_Revision
; values 4 upwards) use Broadcom controller 1 for RISC OS bus 0
; and Broadcom controller 0 for RISC OS bus 1, because the PCB
; layout exchanged the busses.
IIC_Base # 4 ; Base address of IIC controller for RO bus 0
; # 4 ; Base address of IIC controller for RO bus 1
; NOTE - Bus 1 isn't yet implemented!
Timer SETA 0
WHILE Timer < NumTimers
......
......@@ -43,14 +43,16 @@
EXPORT HAL_IICMonitorTransfer
MACRO
$label BaseAddr $r ; Form a pointer to the device's
LDR $r, PeriBase ; base address in register $r
ADD $r, $r, #IIC_Base :AND: :NOT: &FFFF
ADD $r, $r, #IIC_Base :AND: &FFFF
$label BaseAddr $r1, $r2 ; Form a pointer to the device's
LDR $r1, PeriBase ; base address in register $r1
LDR $r2, IIC_Base ; Get the offset to the controller
ADD $r1, $r1, $r2
MEND
; IIC version times 100
IICVersion * 100 ; A guess!
IICVersion * 210 ; A guess! Rev. 2.1
; IIC divider to give 100 kHz
IICDivider * 2496
; Definitions of HAL IIC return codes
IICStatus_Completed * 0
IICStatus_InProgress * 1
......@@ -81,27 +83,41 @@ IIC_DONE * 1 << 1 ; 1 -> Transfer complete
IIC_TA * 1 << 0 ; 1 -> Transfer active
IIC_Init
; Set GPIO0 to SDA and GPIO1 to SCL
DoMemBarrier a2 ; Ensure all peripheral registers
; Choose the controller to use for RISC OS IIC bus 0
LDR a2, Board_Revision ; Read the board revision code
CMP a2, #4 ; Codes 4 upwards denote swapped
MOV a2, #IIC_Base0 :AND: &FFFF; Start with BSC0
ADD a2, a2, #IIC_Base0 :AND: &FFFF0000
MOVHS a2, #IIC_Base1 :AND: &FFFF; If rev code 4 upwards, use BCS1
ADDHS a2, a2, #IIC_Base1 :AND: &FFFF0000
STR a2, IIC_Base ; Store the choice
; Set up output pins of BSC0 and BSC1
; Set GPIO0 to SDA0, GPIO1 to SCL0, GPIO2 to SDA1 and GPIO3 to SCL1
LDR a2, PeriBase
ADD a3, a2, #GPIO_Base
LDR a2, [a3, #GPFSel0] ; Must set GPIO0 and GPIO1 to alt-f0
LDR a2, [a3, #GPFSel0] ; Must set GPIO0..3 to alt-f0
BIC a2, a2, #8_00000077 ; which is binary 100
BIC a2, a2, #8_00007700
ORR a2, a2, #8_00000044
ORR a2, a2, #8_00004400
STR a2, [a3, #GPFSel0]
DoMemBarrier a1 ; Ensure all peripheral registers
; Enable the controller
BaseAddr a4 ; a4 -> IIC controller 0
BaseAddr a4, a1 ; a4 -> IIC controller 0
LDR a1, [a4, #IIC_C] ; a1 = Control reg's contents
ORR a1, a1, #IIC_I2CEN ; Enable the controller
STR a1, [a4, #IIC_C]
MOV a1, #2496 ; Set the clock diider to give a
MOV a1, #IICDivider ; Set the clock divider to give a
STR a1, [a4, #IIC_DIV] ; bus frequency of 100 kHz
DoMemBarrier a1 ; Ensure all peripheral registers
MOV a1, #0
STR a1, IIC_Status ; Say the IIC system is not busy
MOV pc, lr
HAL_IICBuses
MOV a1,#1
MOV pc,lr
MOV a1, #1
MOV pc, lr
HAL_IICType
MOV a1, #(IICVersion << 20); IIC version
......@@ -157,7 +173,8 @@ HAL_IICTransfer
MVN a1, #0 ; Flag us as busy before we go further
STR a1, IIC_Status
STMFD sp!, {v1, v2, v3, v4, v5, lr}
BaseAddr v1 ; v1 -> IIC controller regs
DoMemBarrier lr
BaseAddr v1, lr ; v1 -> IIC controller regs
MOV a1, #IIC_DONE ; Clear the Transfer Done bit
ORR a1, a1, #IIC_CLKTBit :OR: IIC_ERR; and the error flags
STR a1, [v1, #IIC_S] ; by writing 1s to them
......@@ -292,6 +309,7 @@ transfer_OK
MOV a1, #IICStatus_Completed
; This is where we exit:
transfer_exit
DoMemBarrier a2 ; Ensure all peripheral registers
MOV a2, #0 ; No longer busy
STR a2, IIC_Status
LDMFD sp!, {v1, v2, v3, v4, v5, pc}
......
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