Commit 9f19d29e authored by Ben Avison's avatar Ben Avison Committed by ROOL

Support >1GB RAM

RAM sizes above 1GB are not reported by the usual mailbox property, and it
seems unlikely that this will change because the VC RAM allocation has to
remain within the bottom 1GB of the address space (the VC still uses the
upper two bits of its addresses for cache policy) and this property cannot
describe a non-contiguous range. Use the board revision bitfield to recognise
when additional general-purpose RAM exists above the VC allocation. For now,
we're running in "low peripherals" mode, so the top 64MB of 4GB RAM machines
is inaccessible. If the VC allocation is also 64MB, that means the startup
banner of Pi 4 will read 960MB, 1984MB or 3968MB.

Also fix HAL_PhysInfo (and by implication, OS_Memory 6 and 7) to report the
full 35-bit physical address space on Pi 4. The `range` struct filled in by
HAL_PhysInfo has not been extended to 64-bit physical addresses because it
describes RAM, and for now at least, RAM just squeezes into 32-bit addresses.
parent b1569c4f
......@@ -101,6 +101,10 @@ IO_Base2_BCM2838 * &FC000000 ; Pi 4 adds a second range of periph
IO_Size_BCM2835 * &01000000
IO_Size_BCM2838 * &01800000
IO_Size2_BCM2838 * &02000000
PCIe_Base_Hi * &06
PCIe_Base_Lo * &00000000
PCIe_Size_Hi * &02
PCIe_Size_Lo * &00000000
RAM_Base * &00000000 ; try off bottom
Boot_RAM_Base * &00000000
DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes
......
......@@ -123,9 +123,11 @@ FB_CacheMode # 4
; info interrogated from the VC side
ARM_Base # 4
ARM_Size # 4
ARM_End # 4
VC_Base # 4
VC_Size # 4
ARM_Base2 # 4
ARM_End2 # 4
Board_Model # 4
Board_Revision # 4
ARM_DMAChannels # 4
......
......@@ -132,12 +132,28 @@ HAL_QueryPlatform ROUT
ADD r0,r5,#ARMbs-tagb ; ARM address and size
LDMIA r0, {r1, r2}
STR r1, ARM_Base
STR r2, ARM_Size
ADD r2, r1, r2
STR r2, ARM_End
STR r2, ARM_Base2
STR r2, ARM_End2
LDR r0, [r5, #boardmodel-tagb]
LDR r1, [r5, #boardrev-tagb]
LDR r2, [r5, #dmachans-tagb]
STR r0, Board_Model
STR r1, Board_Revision
; Presence and size of second bank of general-purpose RAM has to be
; established from the board revision bitfield
TST r1, #BoardRevision_NewScheme
BEQ %FT01
AND r1, r1, #BoardRevision_Mem_Mask
CMP r1, #BoardRevision_Mem_2G
BLO %FT01
MOV r0, #&40000000
MOVEQ r1, #&80000000
MOVHI r1, #IO_Base2_BCM2838
STR r0, ARM_Base2
STR r1, ARM_End2
01
; If no channels are reported as available, use channel 4
; (Matches default channel mask from Linux)
CMP r2, #0
......
......@@ -319,16 +319,16 @@ start
ALIGN
]
LDR v3, ARM_Base
LDR v4, ARM_Size
LDR v7, ARM_End2
[ HALDebug
ADRL a1, reset
BL HAL_DebugHexTX4
MOV a1, v3
BL HAL_DebugHexTX4
MOV a1, v4
MOV a1, v7
BL HAL_DebugHexTX4
BL HAL_DebugTXStrInline
DCB "ROM start, RAM start, RAM size", 10, 0
DCB "ROM start, RAM start, RAM end", 10, 0
ALIGN
]
relocate_code
......@@ -343,7 +343,6 @@ relocate_code
ADD v2, v2, #OSROM_HALSize ; Size of HAL+OS
ADD lr, lr, #OSROM_HALSize ; Size of compressed HAL+OS
ADD v5, v1, lr ; End of OS
ADD v7, v3, v4 ; End of RAM
SUB ip, v7, v2 ; New start address of HAL
CMP v1, ip
BEQ relocate_10 ; No copy needed
......@@ -432,6 +431,7 @@ clear_ram
; ip is end of RAM/start of ROM
; Note this code will clear the stack, but there shouldn't be anything on it yet anyway
MOV a1, ip
LDR v2, ARM_Base2
MOV a2, #0
MOV a3, #0
MOV a4, #0
......@@ -446,10 +446,16 @@ clear_lp1
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
STMDB a1!,{a2-a4,v1,v4,v5,v7,lr}
TEQ a1, v2
LDREQ a1, ARM_End
CMP a1, v3
BHI clear_lp1
MOV a2, v3
MOV a3, ip
MOV a1, #0 ; AddRAM reference handle (NULL for first call)
Push "a1, ip"
LDR a2, ARM_Base
LDR a3, ARM_End
CMP a3, ip
MOVHI a3, ip
[ HALDebug
BL HAL_DebugTXStrInline
DCB "HalStartup3 .. rst rend",10,0
......@@ -458,13 +464,31 @@ clear_lp1
BL HAL_DebugHexTX4
MOV a1, a3
BL HAL_DebugHexTX4
MOV a1, #0
]
MVN a4, #0
MOV a1, #0
STR a1, [sp, #-4]! ;reference handle (NULL for first call)
CallOSM OS_AddRAM
STR a1, [sp] ; ref for next call
STR a1,[sp] ;ref for next call
MOV a1, #0
LDR a2, ARM_Base2
LDR a3, [sp, #4]
CMP a3, a2
BLS %FT01 ; no second block of RAM
[ HALDebug
BL HAL_DebugTXStrInline
DCB "HalStartup4 .. rst rend",10,0
ALIGN
MOV a1, a2
BL HAL_DebugHexTX4
MOV a1, a3
BL HAL_DebugHexTX4
MOV a1, #0
]
MVN a4, #0
CallOSM OS_AddRAM
STR a1, [sp] ; ref for next call
01
; OS kernel informed of RAM areas
......@@ -473,7 +497,7 @@ clear_lp1
LDR a2, [a2, #PM_RSTS] ; consider reset status
TST a2, #PM_RSTS_HADPOR
LDR a4,[sp],#4 ;!!! ref from last AddRAM
Pull "a4,ip" ; a4 = ref from last AddRAM
MOV a1, #OSStartFlag_RAMCleared
ORRNE a1, a1, #OSStartFlag_POR
ADRL a2, HAL_Base + OSROM_HALSize ; a2 -> RISC OS image
......@@ -774,11 +798,15 @@ HAL_Init
LDR a3, [a4, #:INDEX:VC_Size]
LDR a2, [a4, #:INDEX:VC_Base]
LDR a1, [a4, #:INDEX:ARM_Base]
LDR ip, [a4, #:INDEX:ARM_Size]
LDR ip, [a4, #:INDEX:ARM_End]
STR a3, VC_Size
STR a2, VC_Base
STR a1, ARM_Base
STR ip, ARM_Size
STR ip, ARM_End
LDR a1, [a4, #:INDEX:ARM_Base2]
LDR ip, [a4, #:INDEX:ARM_End2]
STR a1, ARM_Base2
STR ip, ARM_End2
LDR a3, [a4, #:INDEX:Board_Model]
LDR a2, [a4, #:INDEX:Board_Revision]
......@@ -964,11 +992,14 @@ HAL_Reset
HAL_PhysInfo ROUT
TEQ a1, #PhysInfo_GetTableSize
MOVEQ a1, #524288 ; Two pages in each byte, so (2^32)/(4096*2)
STREQ a1, [a2]
MVNEQ a1, #0
MOVEQ pc, lr
BNE %FT01
CPUDetect a2
MOVLS a1, #524288 ; Two pages in each byte, so (2^32)/(4096*2)
MOVHI a1, #4194304 ; Two pages in each byte, so (2^35)/(4096*2)
STR a1, [a2]
MVN a1, #0
MOV pc, lr
01
TEQ a1, #PhysInfo_HardROM
MOVEQ a1, #0 ; No hard ROM
MOVEQ a2, #0
......@@ -982,14 +1013,16 @@ HAL_PhysInfo ROUT
Push "v1-v5,lr"
LDR v1, ARM_Base
LDR v2, ARM_Size
ADD v2, v1, v2
LDR v2, ARM_End2
SUB v2, v2, #1 ; make inclusive
STMIA a3, {v1-v2} ; All RAM the OS knows about will be here
; Majority of table is unused, so prefill it
LDR v3, =&88888888 ; Unused regions (or RAM)
MOV a1, v3
MOV a3, v3
MOV a4, v3
CPUDetect v5
BHI Pi4_PhysInfo
ADD v4, a2, #524288
10
STMIA a2!, {a1,a3,a4,v3}
......@@ -999,7 +1032,6 @@ HAL_PhysInfo ROUT
CPUDetect v5
SUB a2, a2, #524288-(IO_Base_BCM2835>>13)
ADDEQ a2, a2, #(IO_Base_BCM2836-IO_Base_BCM2835)>>13
ADDHI a2, a2, #(IO_Base2_BCM2838-IO_Base_BCM2835)>>13
ORR a1, a1, a1, LSR #1 ; Pattern for IO regions
ORR a3, a3, a3, LSR #1
ORR a4, a4, a4, LSR #1
......@@ -1007,9 +1039,6 @@ HAL_PhysInfo ROUT
ADDLO v5, a2, #IO_Size_BCM2835>>13
ASSERT IO_Base_BCM2836+IO_Size_BCM2835 = INT_BASE_BCM2836
ADDEQ v5, a2, #(IO_Size_BCM2835+INT_SIZE)>>13
ASSERT IO_Base2_BCM2838+IO_Size2_BCM2838 = IO_Base_BCM2838
ASSERT IO_Base_BCM2838+IO_Size_BCM2838 = INT_BASE_BCM2838
ADDHI v5, a2, #(IO_Size2_BCM2838+IO_Size_BCM2838+INT_SIZE)>>13
ASSERT INT_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
20
STMIA a2!, {a1,a3,a4,v3}
......@@ -1028,6 +1057,45 @@ HAL_PhysInfo ROUT
MVN a1, #0
Pull "v1-v5,pc"
Pi4_PhysInfo
ADD v4, a2, #4194304
10
STMIA a2!, {a1,a3,a4,v3}
CMP a2, v4
BLO %BT10
; Fill in IO region
SUB a2, a2, #4194304
ADD a2, a2, #IO_Base2_BCM2838>>13
ORR a1, a1, a1, LSR #1 ; Pattern for IO regions
ORR a3, a3, a3, LSR #1
ORR a4, a4, a4, LSR #1
ORR v3, v3, v3, LSR #1
ADD v5, a2, #(IO_Size2_BCM2838+IO_Size_BCM2838+INT_SIZE)>>13
ASSERT INT_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
20
STMIA a2!, {a1,a3,a4,v3}
CMP a2, v5
BLO %BT20
; VC memory is effectively IO, so fill it in as such
SUB a2, v4, #4194304
LDR v1, VC_Base
LDR v2, VC_Size
ADD a2, a2, v1, LSR #13
ADD v5, a2, v2, LSR #13
30
STMIA a2!, {a1,a3,a4,v3}
CMP a2, v5
BLO %BT30
; Pi 4 features a PCIe bus in the top 8 GB, fill it in as IO too
SUB a2, v4, #4194304-((PCIe_Base_Hi<<(32-13)) + (PCIe_Base_Lo>>13))
ASSERT 4194304 = ((PCIe_Base_Hi + PCIe_Size_Hi)<<(32-13)) + ((PCIe_Base_Lo + PCIe_Size_Lo)>>13)
40
STMIA a2!, {a1,a3,a4,v3}
CMP a2, v4
BLO %BT40
MVN a1, #0
Pull "v1-v5,pc"
HAL_Null
MOV pc, lr
......
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