Commit 985c7199 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add DMA driver

Detail:
  s/DMA, hdr/DMA, Makefile - DMA driver, as an implementation of the DMA controller and list type DMA channel HAL devices
  hdr/StaticWS - Added DMA workspace definition
  hdr/BCM2835 - Removed DMA control block definition (now in hdr/DMA). Add definitions for the mailbox property interface, which should be supported by the GPU firmware sometime soon.
  s/Top - Export a couple of the debug functions. Store logical & physical address of NCNB workspace instead of hackily getting phys addr of the (cacheable) HAL workspace. Call DMA_InitDevices in HAL_InitDevices.
Admin:
  Tested in BCM2835 ROM
  DMA driver hasn't received large amounts of testing, lacks support for finite-length circular transfers, and currently only has one DMA channel enabled
  More DMA channels should be available once the mailbox property interface is functional and we know which channels the GPU does and doesn't use.


Version 0.11. Tagged as 'BCM2835-0_11'
parent 60ebea68
......@@ -17,7 +17,7 @@
COMPONENT = BCM2835 HAL
TARGET = BCM2835
OBJS = Top CLib CMOS Debug Display Interrupts SDIO Stubs Timers UART USB Video
OBJS = Top CLib CMOS Debug Display Interrupts SDIO Stubs Timers UART USB Video DMA
HDRS =
CMHGFILE =
......
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.10"
Module_Version SETA 10
Module_MajorVersion SETS "0.11"
Module_Version SETA 11
Module_MinorVersion SETS ""
Module_Date SETS "01 Jul 2012"
Module_ApplicationDate SETS "01-Jul-12"
Module_Date SETS "07 Jul 2012"
Module_ApplicationDate SETS "07-Jul-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.10"
Module_HelpVersion SETS "0.10 (01 Jul 2012)"
Module_FullVersion SETS "0.11"
Module_HelpVersion SETS "0.11 (07 Jul 2012)"
END
/* (0.10)
/* (0.11)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.10
#define Module_MajorVersion_CMHG 0.11
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 01 Jul 2012
#define Module_Date_CMHG 07 Jul 2012
#define Module_MajorVersion "0.10"
#define Module_Version 10
#define Module_MajorVersion "0.11"
#define Module_Version 11
#define Module_MinorVersion ""
#define Module_Date "01 Jul 2012"
#define Module_Date "07 Jul 2012"
#define Module_ApplicationDate "01-Jul-12"
#define Module_ApplicationDate "07-Jul-12"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.10"
#define Module_HelpVersion "0.10 (01 Jul 2012)"
#define Module_LibraryVersionInfo "0:10"
#define Module_FullVersion "0.11"
#define Module_HelpVersion "0.11 (07 Jul 2012)"
#define Module_LibraryVersionInfo "0:11"
......@@ -244,6 +244,8 @@ MB_Chan_VCHIQ * 3 ; VCHIQ channel
MB_Chan_LEDS * 4 ; LEDS channel
MB_Chan_Btn * 5 ; Buttons channel
MB_Chan_TSc * 6 ; TouchScreen channel
MB_Chan_ARM2VC * 8 ; ARM -> VC property channel
MB_Chan_VC2ARM * 9 ; VC -> ARM property channel
; far end replies on the same channel when command done.. e.g.
; command c0000001 gets 00000001 (ie channel1) reply
; Power channel bits
......@@ -256,6 +258,55 @@ MB_Pwr_I2C1_MASK * 5
MB_Pwr_I2C2_MASK * 6
MB_Pwr_SPI_MASK * 7
MB_Pwr_CCP2TX_MASK * 8
; ARM2VC tags
; see https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
; Note - this interface isn't implemented in the GPU firmware yet!
ARM2VC_Tag_End * &00000000 ; End of tag list
ARM2VC_Tag_GetFirmwareVersion * &00000001 ; return 4 byte firmware version
ARM2VC_Tag_GetBoardModel * &00010001 ; return 4 byte model
ARM2VC_Tag_GetBoardRevision * &00010002 ; return 4 byte revision
ARM2VC_Tag_GetBoardMAC * &00010003 ; return 6 byte MAC
ARM2VC_Tag_GetBoardSerial * &00010004 ; return 8 byte serial
ARM2VC_Tag_GetARMMemory * &00010005 ; return ARM mem base + size
ARM2VC_Tag_GetVCMemory * &00010006 ; return VC mem base + size
ARM2VC_Tag_GetClocks * &00010007 ; return clock tree
ARM2VC_Tag_GetConfig * &00050001 ; get kernel boot args string
ARM2VC_Tag_GetDMAChannels * &00060001 ; get mask of DMA channels usable by ARM
ARM2VC_Tag_GetPowerState * &00020001 ; get power state of specified MB_Pwr_ device
ARM2VC_Tag_GetPowerTiming * &00020002 ; get microsecond delay required after power on for indicated device
ARM2VC_Tag_SetPowerState * &00028001 ; set power state of device
ARM2VC_Tag_GetClockState * &00030001 ; get power state of clock
ARM2VC_Tag_SetClockState * &00038001 ; set power state of clock
ARM2VC_Tag_GetClockRate * &00030002 ; get rate of clock
ARM2VC_Tag_SetClockRate * &00038002 ; set rate of clock
ARM2VC_Tag_FBAlloc * &00040001 ; alloc framebuffer at given alignment
ARM2VC_Tag_FBRelease * &00048001 ; release framebuffer
ARM2VC_Tag_FBBlank * &00040002 ; blank screen
ARM2VC_Tag_FBGetPhysDimension * &00040003 ; get physical display width/height
ARM2VC_Tag_FBTestPhysDimension * &00044003 ; test physical display w/h
ARM2VC_Tag_FBSetPhysDimension * &00048003 ; set physical display w/h
ARM2VC_Tag_FBGetVirtDimension * &00040004 ; get virtual display w/h
ARM2VC_Tag_FBTestVirtDimension * &00044004 ; test virtual display w/h
ARM2VC_Tag_FBSetVirtDimension * &00048004 ; set virtual display w/h
ARM2VC_Tag_FBGetDepth * &00040005 ; get display BPP
ARM2VC_Tag_FBTestDepth * &00044005 ; test display BPP
ARM2VC_Tag_FBSetDepth * &00048005 ; set display BPP
ARM2VC_Tag_FBGetPixelOrder * &00040006 ; get RGB/BGR order
ARM2VC_Tag_FBTestPixelOrder * &00044006 ; test RGB/BGR order
ARM2VC_Tag_FBSetPixelOrder * &00048006 ; set RGB/BGR order
ARM2VC_Tag_FBGetAlphaMode * &00040007 ; get alpha mode
ARM2VC_Tag_FBTestAlphaMode * &00044007 ; test alpha mode
ARM2VC_Tag_FBSetAlphaMode * &00048007 ; set alpha mode
ARM2VC_Tag_FBGetPitch * &00040008 ; get row pitch
ARM2VC_Tag_FBGetVirtOffset * &00040009 ; get X/Y offset of virtual display
ARM2VC_Tag_FBTestVirtOffset * &00044009 ; test X/Y offset
ARM2VC_Tag_FBSetVirtOffset * &00048009 ; set X/Y offset
ARM2VC_Tag_FBGetOverscan * &0004000a ; get overscan values
ARM2VC_Tag_FBTestOverscan * &0004400a ; test overscan values
ARM2VC_Tag_FBSetOverscan * &0004800a ; set overscan values
ARM2VC_Tag_FBGetPalette * &0004000b ; get full palette table
ARM2VC_Tag_FBTestPalette * &0004400b ; test ranged update of table
ARM2VC_Tag_FBSetPalette * &0004800b ; do ranged update of table
; mem barrier operation; ensures all explicit mem operations completed before
......@@ -391,24 +442,9 @@ ST_C3 * &18 ; compare 3
ARM_Timer_Base * &0000b400 ; base of ARM timer regs
; DMA registers
DMA_Base * &00007000 ;
DMA0_CS * 0
DMA0_CONBLK_AD * 4
DMA0_DEBUG * &20
; DMA control block
^ 0
DMAcb_info # 4
DMAcb_src # 4
DMAcb_dst # 4
DMAcb_length # 4
DMAcb_stride # 4
DMAcb_next # 4
DMAcb_pad0 # 4
DMAcb_pad1 # 4
sizeof_DMAcb * @
DMA_Base * &00007000
DMA_CH_Count * 13 ; Allegedly 16 channels, but can only get IRQs from 13 of them?
;
PM_Base * &00100000 ; power management
......
;
; Copyright (c) 2012, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; General registers, from DMA_Base
DMA_INT_STATUS * &fe0
DMA_ENABLE * &ff0
; DMA control block
^ 0
DMACB_TI # 4
DMACB_SOURCE_AD # 4
DMACB_DEST_AD # 4
DMACB_TXFR_LEN # 4
DMACB_STRIDE # 4
DMACB_NEXTCONBK # 4
DMACB_RESERVED # 8
DMACB_SIZE * @
DMACB_ALIGN * 32
; DMA channel register map
^ 0
DMACH_CS # 4 ; RW
DMACH_CONBLK_AD # 4 ; RW
DMACH_TI # 4 ; RO
DMACH_SOURCE_AD # 4 ; RO
DMACH_DEST_AD # 4 ; RO
DMACH_TXFR_LEN # 4 ; RO
DMACH_STRIDE # 4 ; RO
DMACH_NEXTCONBK # 4 ; RO (RW when paused)
DMACH_DEBUG # 4 ; RW
; Stride of 256 bytes between each channel
DMA_CH_STRIDE * &100
; Register/CB bits
DMA_CS_RESET * 1<<31
DMA_CS_ABORT * 1<<30
DMA_CS_DISDEBUG * 1<<29
DMA_CS_WAIT_FOR_OUTSTANDING_WRITES * 1<<28
DMA_CS_PANIC_PRIORITY_SHIFT * 20
DMA_CS_PANIC_PRIORITY_MASK * &F
DMA_CS_PRIORITY_SHIFT * 16
DMA_CS_PRIORITY_MASK * &F
DMA_CS_ERROR * 1<<8
DMA_CS_WAITING_FOR_OUTSTANDING_WRITES * 1<<6
DMA_CS_DREQ_STOPS_DMA * 1<<5
DMA_CS_PAUSED * 1<<4
DMA_CS_DREQ * 1<<3
DMA_CS_INT * 1<<2
DMA_CS_END * 1<<1
DMA_CS_ACTIVE * 1<<0
DMA_TI_NO_WIDE_BURSTS * 1<<26
DMA_TI_WAITS_SHIFT * 21
DMA_TI_WAITS_MASK * &F
DMA_TI_PERMAP_SHIFT * 16
DMA_TI_PERMAP_MASK * &1F
DMA_TI_BURST_LENGTH_SHIFT * 12
DMA_TI_BURST_LENGTH_MASK * &F
DMA_TI_SRC_IGNORE * 1<<11
DMA_TI_SRC_DREQ * 1<<10
DMA_TI_SRC_WIDTH * 1<<9
DMA_TI_SRC_INC * 1<<8
DMA_TI_DEST_IGNORE * 1<<7
DMA_TI_DEST_DREQ * 1<<6
DMA_TI_DEST_WIDTH * 1<<5
DMA_TI_DEST_INC * 1<<4
DMA_TI_WAIT_RESP * 1<<3
DMA_TI_TDMODE * 1<<1 ; Not in lite channels
DMA_TI_INTEN * 1<<0
DMA_TXFR_LEN_YLENGTH_SHIFT * 16 ; Not in lite channels
DMA_TXFR_LEN_YLENGTH_MASK * &3FFF
DMA_TXFR_LEN_XLENGTH_SHIFT * 0
DMA_TXFR_LEN_XLENGTH_MASK * &FFFF
DMA_TXFR_LEN_D_STRIDE_SHIFT * 16
DMA_TXFR_LEN_D_STRIDE_MASK * &FFFF
DMA_TXFR_LEN_S_STRIDE_SHIFT * 16
DMA_TXFR_LEN_S_STRIDE_MASK * &FFFF
DMA_DEBUG_LITE * 1<<28
DMA_DEBUG_VERSION_SHIFT * 25
DMA_DEBUG_VERSION_MASK * &7
DMA_DEBUG_DMA_STATE_SHIFT * 16
DMA_DEBUG_DMA_STATE_MASK * &FF
DMA_DEBUG_DMA_ID_SHIFT * 8
DMA_DEBUG_DMA_ID_MASK * &FF
DMA_DEBUG_OUTSTANDING_WRITES_SHIFT * 4
DMA_DEBUG_OUTSTANDING_WRITES_MASK * &F
DMA_DEBUG_READ_ERROR * 1<<2
DMA_DEBUG_FIFO_ERROR * 1<<1
DMA_DEBUG_READ_LAST_NOT_SET_ERROR * 1<<0
; Peripheral DREQ values
DREQ_NONE * 0
DREQ_DSI1 * 1
DREQ_PCM_TX * 2
DREQ_PCM_RX * 3
DREQ_SMI * 4
DREQ_PWM * 5
DREQ_SPI_TX * 6
DREQ_SPI_RX * 7
DREQ_BSC_SPI_SLAVE_TX * 8
DREQ_BSC_SPI_SLAVE_RX * 9
DREQ_EMMC * 11
DREQ_UART_TX * 12
DREQ_SD_HOST * 13
DREQ_UART_RX * 14
DREQ_DSI2 * 15
DREQ_SLIMBUS_MC_TX * 16
DREQ_HDMI * 17
DREQ_SLIMBUS_MC_RX * 18
DREQ_SLIMBUS_DC0 * 19
DREQ_SLIMBUS_DC1 * 20
DREQ_SLIMBUS_DC2 * 21
DREQ_SLIMBUS_DC3 * 22
DREQ_SLIMBUS_DC4 * 23
DREQ_SCALER_FIFO_0_SMI * 24
DREQ_SCALER_FIFO_1_SMI * 25
DREQ_SCALER_FIFO_2_SMI * 26
DREQ_SLIMBUS_DC5 * 27
DREQ_SLIMBUS_DC6 * 28
DREQ_SLIMBUS_DC7 * 29
DREQ_SLIMBUS_DC8 * 30
DREQ_SLIMBUS_DC9 * 31
; Channels 7-14 are lite channels
DMA_CH_is_lite * &7F80
END
......@@ -33,6 +33,7 @@
GET Hdr:OSEntries
GET Hdr:HALDevice
GET Hdr:SDHCIDevice
GET Hdr:DMADevice
GET hdr.BCM2835
; Per-timer workspace layout
......@@ -43,6 +44,21 @@ Timer_Register # 4 ; address of compare register
Timer_Device # 4 ; device number
TimerWsSize * :INDEX: @
; Per-DMA channel workspace
^ 0, a1
DMACDevice # HALDevice_DMAL_Size
DMACWorkspace # 4 ; HAL workspace ptr
DMACChanMask # 4 ; DMA_ENABLE bit for this channel
DMACDREQ # 4 ; Peripheral/DREQ this channel is servicing
DMACOptions # 4 ; Options set by SetOptions
DMACPeriAddress # 4 ; VC phys addr of peripheral - i.e. at &7e......
DMACLastProgress # 4 ; Last progress value
DMACLastCONBLK_AD # 4 ; Last control block seen executing
DMACLastTXFR_LEN # 4 ; Last transfer length remaining seen
DMACCBOffset # 4 ; Address offset to convert DMA CB addr to ARM CB addr
DMACDesc # 32 ; Buffer for description string
DMAC_DeviceSize * :INDEX: @
; Main workspace layout
......@@ -56,8 +72,6 @@ ARM_Counter_IO_Address # 4
ARM_Timer_IO_Address # 4
UARTFCRSoftCopy # 4
DMAcb # sizeof_DMAcb
Timer SETA 0
WHILE Timer < NumTimers
Timer$Timer.Ws # TimerWsSize
......@@ -105,7 +119,8 @@ CurAddr # 4
CurHeight # 4
CurPalette # 4*4
WSPhysAddr # 4 ;physical address of HAL workspace
NCNBAddr # 4 ;NCNB workspace
NCNBPhysAddr # 4 ;VC physical address of NCNB workspace
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
......@@ -118,6 +133,13 @@ SDHCIInputClock # 4 ; estimated speed of input clock to SDHCI block
SDHCIDevice # HALDevice_SDHCISize ; see Hdr:SDHCIDevice
SDHCISlotInfo # HALDeviceSDHCI_SlotInfo_Size ; the controller has just the 1 slot
DMAFreeChannels # 4 ; Mask of which physical DMA channels are free
DMANumChannels # 4 ; Count of how many channel devices exist
DMAChannelList # DMA_CH_Count*4 ; List of channel devices for Enumerate
# (16-:INDEX:@):AND:15 ; align nicely
DMAController # HALDevice_DMAC_Size_0_1 ; see Hdr:HALDevice
DMAChannels # DMAC_DeviceSize*DMA_CH_Count ; List of channel devices (indexed by physical channel #)
CurUnder # 32*4*32
CurShape # 32/4*32
......
This diff is collapsed.
......@@ -143,6 +143,8 @@
IMPORT SDIO_InitDevices
IMPORT DMA_InitDevices
EXPORT HAL_Base
HAL_Base
......@@ -155,6 +157,8 @@ HAL_Base
IMPORT output_regs
IMPORT output_text
IMPORT output_text_at
EXPORT HAL_DebugHexTX4
EXPORT HAL_DebugTXStrInline
]
EXPORT reset
......@@ -769,16 +773,15 @@ HAL_Init
STR a2, FB_Base ; for HAL_FramestoreAddress use
STR a1, FB_CacheMode
; Get the physical address of the start of our workspace
; R8 -> start of the page containing our workspace
; Get the physical address of NCNB workspace
; R8 -> start of NCNB workspace
STR R8, NCNBAddr
MOV a1,R8
CallOS OS_LogToPhys
MOV a2, sb, LSL #20
LDR a3, FB_CacheMode
ORR a1, a1, a3;#DMA_RAM_Base
ORR a1, a1, a2, LSR #20 ; factor in start offset
STR a1, WSPhysAddr
ORR a1, a1, a3
STR a1, NCNBPhysAddr
MOV a1, #0 ; map in the IO space
LDR a2, =IO_Base
......@@ -943,6 +946,7 @@ HAL_Null
HAL_InitDevices
STR lr, [sp, #-4]!
BL SDIO_InitDevices
BL DMA_InitDevices
LDR pc, [sp], #4
......
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