Commit 9115b479 authored by ROOL's avatar ROOL 🤖
Browse files

Move the board rev definitions into hdr

Detail:
  Useful if not just SDIO can see the definitions.

Version 0.62. Tagged as 'BCM2835-0_62'
parent afc8ef8d
/* (0.61)
/* (0.62)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.61
#define Module_MajorVersion_CMHG 0.62
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 15 Oct 2016
#define Module_Date_CMHG 22 Oct 2016
#define Module_MajorVersion "0.61"
#define Module_Version 61
#define Module_MajorVersion "0.62"
#define Module_Version 62
#define Module_MinorVersion ""
#define Module_Date "15 Oct 2016"
#define Module_Date "22 Oct 2016"
#define Module_ApplicationDate "15-Oct-16"
#define Module_ApplicationDate "22-Oct-16"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.61"
#define Module_HelpVersion "0.61 (15 Oct 2016)"
#define Module_LibraryVersionInfo "0:61"
#define Module_FullVersion "0.62"
#define Module_HelpVersion "0.62 (22 Oct 2016)"
#define Module_LibraryVersionInfo "0:62"
......@@ -290,6 +290,54 @@ $label BIC$cond $startaddr, $startaddr, #&1f
MCRR$cond p15, 0, $endaddr, $startaddr, c14
]
MEND
; Board revision values (pre Pi 2), enumerated scheme
; Ref: http://elinux.org/RPi_HardwareHistory#Board_Revision_History
BoardRevision_AorB256_First * &2 ; } Either an A or B
BoardRevision_AorB256_Last * &9 ; } various manufacturers
BoardRevision_AorB512_First * &D ; } Either an A or B
BoardRevision_AorB512_Last * &F ; } various manufacturers
BoardRevision_AorB_First * &2 ; } Either an A or B, 256MB or 512MB
BoardRevision_AorB_Last * &F ; } and various manufacturers
BoardRevision_BPlus * &10 ; Significant board revisions
BoardRevision_Compute * &11
BoardRevision_APlus * &12
; Board revision values (Pi 2 and later), bitfield scheme
BoardRevision_User_Shift * 24
BoardRevision_User_Mask * 255 :SHL: BoardRevision_User_Shift
BoardRevision_Warranty * 1 :SHL: 25 ; if set, warranty void (Pi 2 and later)
BoardRevision_WarrantyOld * 1 :SHL: 24 ; if set, warranty void (pre Pi 2)
BoardRevision_NewScheme * 1 :SHL: 23 ; if set, indicates the following are in use
BoardRevision_Mem_Shift * 20
BoardRevision_Mem_Mask * 7 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_256M * 0 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_512M * 1 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_1G * 2 :SHL: BoardRevision_Mem_Shift
BoardRevision_Manuf_Shift * 16
BoardRevision_Manuf_Mask * 15 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Manuf_Sony * 0 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Manuf_Egoman * 1 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Manuf_Embest * 2 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Manuf_Embest2 * 4 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Proc_Shift * 12
BoardRevision_Proc_Mask * 15 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2835 * 0 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2836 * 1 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2837 * 2 :SHL: BoardRevision_Proc_Shift
BoardRevision_Model_Shift * 4
BoardRevision_Model_Mask * 255 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_A * 0 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_B * 1 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_APlus * 2 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_BPlus * 3 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_B2 * 4 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_Compute * 6 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_B3 * 8 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_Zero * 9 :SHL: BoardRevision_Model_Shift
BoardRevision_Rev_Shift * 0
BoardRevision_Rev_Mask * 15 :SHL: BoardRevision_Rev_Shift
; GPIO register set
GPIO_Base * &00200000 ; base offset of GPIO regs
GPFSel0 * &0 ; function sel 0
......
......@@ -57,36 +57,6 @@ REGISTER_WRITE_PACE * 2
; writes while reprogramming SDCLK
MIN_SDCLK * 400
; Significant board revisions
BoardRevision_BPlus * &10
BoardRevision_Compute * &11
BoardRevision_APlus * &12
; Starting with the Pi 2, board revisions have changed to a bitfield scheme:
BoardRevision_NewScheme * 1 :SHL: 23 ; if set, indicates the following are in use
BoardRevision_Mem_256M * 0 :SHL: 20
BoardRevision_Mem_512M * 1 :SHL: 20
BoardRevision_Mem_1G * 2 :SHL: 20
BoardRevision_Mem_Mask * 7 :SHL: 20
BoardRevision_Manuf_Sony * 0 :SHL: 16
BoardRevision_Manuf_Egoman * 1 :SHL: 16
BoardRevision_Manuf_Embest * 2 :SHL: 16
BoardRevision_Manuf_Embest2 * 4 :SHL: 16
BoardRevision_Manuf_Mask * 15 :SHL: 16
BoardRevision_Proc_2835 * 0 :SHL: 12
BoardRevision_Proc_2836 * 1 :SHL: 12
BoardRevision_Proc_2837 * 2 :SHL: 12
BoardRevision_Proc_Mask * 15 :SHL: 12
BoardRevision_Model_A * 0 :SHL: 4
BoardRevision_Model_B * 1 :SHL: 4
BoardRevision_Model_APlus * 2 :SHL: 4
BoardRevision_Model_BPlus * 3 :SHL: 4
BoardRevision_Model_B2 * 4 :SHL: 4
BoardRevision_Model_Compute * 6 :SHL: 4
BoardRevision_Model_B3 * 8 :SHL: 4
BoardRevision_Model_Zero * 9 :SHL: 4
BoardRevision_Model_Mask * 255 :SHL: 4
BoardRevision_Rev_Mask * 15 :SHL: 0
; Base address of controller as an offset from PeriBase
EMMC_Base * &00300000
......@@ -356,7 +326,7 @@ SDIO_InitDevices ROUT
BL memcpy
LDR a3, Board_Revision
BIC a3, a3, #&FF000000 ; mask off overclocking / user bits
BIC a3, a3, #BoardRevision_User_Mask ; mask off overclocking / user bits
TST a3, #BoardRevision_NewScheme
BNE %FT01
CMP a3, #BoardRevision_BPlus
......
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