Commit 56779d91 authored by Jeffrey Lee's avatar Jeffrey Lee

Put the other cores into a holding pattern

Detail:
  s/Top - On multi-core chips, the ARM boot stub has the other cores sat waiting in a loop near &0. Clearing RAM will inadvertantly break them out of this and most likely cause random crashes later on, so inbetween relocating the ROM and clearing RAM make sure we put the cores into a sleep loop in the HAL. Further mailbox writes can then be used to break them out of this loop, using a similar scheme to that used to break them out of the boot stub loop.
  hdr/BCM2835 - Add some register definitions from the BCM2836 docs
Admin:
  Tested on Pi 2B, 3B
  Not currently dealing with kernel_old=1 case where all cores enter the ROM on startup


Version 0.55. Tagged as 'BCM2835-0_55'
parent 3e87de33
/* (0.54)
/* (0.55)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.54
#define Module_MajorVersion_CMHG 0.55
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 26 Mar 2016
#define Module_Date_CMHG 28 Mar 2016
#define Module_MajorVersion "0.54"
#define Module_Version 54
#define Module_MajorVersion "0.55"
#define Module_Version 55
#define Module_MinorVersion ""
#define Module_Date "26 Mar 2016"
#define Module_Date "28 Mar 2016"
#define Module_ApplicationDate "26-Mar-16"
#define Module_ApplicationDate "28-Mar-16"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.54"
#define Module_HelpVersion "0.54 (26 Mar 2016)"
#define Module_LibraryVersionInfo "0:54"
#define Module_FullVersion "0.55"
#define Module_HelpVersion "0.55 (28 Mar 2016)"
#define Module_LibraryVersionInfo "0:55"
......@@ -544,6 +544,70 @@ IIC_DIV * &14 ; Clock Divider
IIC_DEL * &18 ; Data Delay
IIC_CLKT * &1C ; Clock Stretch Timeout
; ARM control registers for quad core chips (BCM2836, BCM2837, etc.)
; ref: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
QA7_BASE * &40000000
QA7_CONTROL * &0000
QA7_CORE_TIMER_PRESCALE * &0008
QA7_GPU_INT_ROUTING * &000C
QA7_PMU_INT_ROUT_SET * &0010
QA7_PMU_INT_ROUT_CLR * &0014
QA7_CORE_TIMER_LSW * &001C
QA7_CORE_TIMER_MSW * &0020
QA7_LOCAL_INT_ROUTING * &0024
QA7_AXI_OUTSTANDING_CNT * &002C
QA7_AXI_OUTSTANDING_IRQ * &0030
QA7_LOCAL_TIMER_CTRL_STAT * &0034
QA7_LOCAL_TIMER_WRFLAGS * &0038
QA7_CORE0_TIMER_INT_CTRL * &0040
QA7_CORE1_TIMER_INT_CTRL * &0044
QA7_CORE2_TIMER_INT_CTRL * &0048
QA7_CORE3_TIMER_INT_CTRL * &004C
QA7_CORE0_MBOX_INT_CTRL * &0050
QA7_CORE1_MBOX_INT_CTRL * &0054
QA7_CORE2_MBOX_INT_CTRL * &0058
QA7_CORE3_MBOX_INT_CTRL * &005C
QA7_CORE0_IRQ_SOURCE * &0060
QA7_CORE1_IRQ_SOURCE * &0064
QA7_CORE2_IRQ_SOURCE * &0068
QA7_CORE3_IRQ_SOURCE * &006C
QA7_CORE0_FIQ_SOURCE * &0070
QA7_CORE1_FIQ_SOURCE * &0074
QA7_CORE2_FIQ_SOURCE * &0078
QA7_CORE3_FIQ_SOURCE * &007C
QA7_CORE0_MBOX0_SET * &0080 ; Write to set bits in mailbox
QA7_CORE0_MBOX1_SET * &0084
QA7_CORE0_MBOX2_SET * &0088
QA7_CORE0_MBOX3_SET * &008C
QA7_CORE1_MBOX0_SET * &0090
QA7_CORE1_MBOX1_SET * &0094
QA7_CORE1_MBOX2_SET * &0098
QA7_CORE1_MBOX3_SET * &009C
QA7_CORE2_MBOX0_SET * &00A0
QA7_CORE2_MBOX1_SET * &00A4
QA7_CORE2_MBOX2_SET * &00A8
QA7_CORE2_MBOX3_SET * &00AC
QA7_CORE3_MBOX0_SET * &00B0
QA7_CORE3_MBOX1_SET * &00B4
QA7_CORE3_MBOX2_SET * &00B8
QA7_CORE3_MBOX3_SET * &00BC
QA7_CORE0_MBOX0_RDCLR * &00C0 ; Write to clear bits in mailbox
QA7_CORE0_MBOX1_RDCLR * &00C4
QA7_CORE0_MBOX2_RDCLR * &00C8
QA7_CORE0_MBOX3_RDCLR * &00CC
QA7_CORE1_MBOX0_RDCLR * &00D0
QA7_CORE1_MBOX1_RDCLR * &00D4
QA7_CORE1_MBOX2_RDCLR * &00D8
QA7_CORE1_MBOX3_RDCLR * &00DC
QA7_CORE2_MBOX0_RDCLR * &00E0
QA7_CORE2_MBOX1_RDCLR * &00E4
QA7_CORE2_MBOX2_RDCLR * &00E8
QA7_CORE2_MBOX3_RDCLR * &00EC
QA7_CORE3_MBOX0_RDCLR * &00F0
QA7_CORE3_MBOX1_RDCLR * &00F4
QA7_CORE3_MBOX2_RDCLR * &00F8
QA7_CORE3_MBOX3_RDCLR * &00FC
MACRO
$label ReadINTCTL $r,$cond
$label MRC$cond p6, 0, $r, c0, c0
......
......@@ -341,6 +341,53 @@ relocate_10
ALIGN
]
; If we're a multi-core chip, the other cores should be sat in a boot
; stub located at &0, waiting for us to give them the address of some
; code to execute. Move them into a holding space in the relocated ROM
; so that we don't break them when we overwrite the boot stub.
MRC p15, 0, lr, c0, c0, 0 ; read Main ID Register
AND lr, lr, #&FF00
CMP lr, #&C000 ; xxxxB76x for ARM1176, xxxxC07x for Cortex-A7
BCC clear_ram
LDR a1, =QA7_BASE
MVN a2, #0
STR a2, [a1, #QA7_CORE0_MBOX1_RDCLR] ; Clear our mailboxes
STR a2, [a1, #QA7_CORE0_MBOX2_RDCLR]
STR a2, [a1, #QA7_CORE0_MBOX3_RDCLR]
DSB
ADR a2, holding_pattern
STR a2, [a1, #QA7_CORE1_MBOX3_SET] ; Each core is sat waiting for mailbox 3
STR a2, [a1, #QA7_CORE2_MBOX3_SET]
STR a2, [a1, #QA7_CORE3_MBOX3_SET]
DSB
SEV ; Current boot stub just has the cores in a spin loop, but use SEV just in case future stubs are more power-conscious
; Now wait for the cores to acknowledge the request (input via our mailboxes)
MOV a3, #1<<20 ; Timeout
MOV a4, #QA7_CORE0_MBOX1_RDCLR
10
SUBS a3, a3, #1
BEQ %FT20
LDR a2, [a1, a4]
CMP a2, #0
BEQ %BT10
CMP a4, #QA7_CORE0_MBOX3_RDCLR
ADDNE a4, a4, #QA7_CORE0_MBOX2_RDCLR-QA7_CORE0_MBOX1_RDCLR
BNE %BT10
[ HALDebug
BL HAL_DebugTXStrInline
DCB "Aux cores in holding pattern", 10, 0
ALIGN
B %FT25
]
20
[ HALDebug
BL HAL_DebugTXStrInline
DCB "Failed waking cores", 10, 0
ALIGN
25
]
clear_ram
; Clear RAM
; v3 is start of RAM
; ip is end of RAM/start of ROM
......@@ -397,6 +444,45 @@ start_os = "Starting OS",13,10,0
ALIGN
]
holding_pattern
; Auxilliary cores arrive here
; First, work out who we are
MRC p15, 0, a1, c0, c0, 5 ; Read MPIDR
AND a1, a1, #3 ; Extract core number (should be 1-3)
[ HALDebug
DSB
LDR a2, =IO_Base_BCM2836+UART_Base
ADD a3, a1, #'0'
STRB a3, [a2, #UARTDR]
]
DSB
; Clear our mailbox register
LDR a2, =QA7_BASE
ADD a3, a2, #QA7_CORE0_MBOX0_SET
ADD a3, a3, a1, LSL #2 ; Box to reply to core 0 on
ADD a4, a2, #QA7_CORE0_MBOX3_RDCLR
ADD a4, a4, a1, LSL #4 ; Box to receive instructions via
MVN v1, #0
STR v1, [a4]
DSB
; Let the master core know that we're here
STR pc, [a3] ; Any non-zero should do
; Now wait for further instruction
10
WFE
LDR v1, [a2]
CMP v1, #0
BEQ %BT10
[ HALDebug
DSB
LDR a2, =IO_Base_BCM2836+UART_Base
ADD a3, a1, #'0'
STRB a3, [a2, #UARTDR]
]
BX v1
LTORG
HALdescriptor DATA
DCD HALFlag_NCNBWorkspace
DCD HAL_Base - HALdescriptor
......
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