Correct a couple of comments

Some misleading notes about IIC0, and other minor clarifications.

s/IIC

@@ -48,7 +48,7 @@ $label  BaseAddr  $r1, $r2           ; Form a pointer to the device's
         MEND
 
 ; IIC version times 100
-IICVersion             * 210         ; A guess!  Rev. 2.1
+IICVersion             * 210         ; Rev. 2.1, from section 3.1 of BCM2835 ARM Peripherals
 ; IIC divider to give 100 kHz
 IICDivider             * 2496
 ; Definitions of RISC OS IIC flags in iic_transfer structure
@@ -80,25 +80,25 @@ IIC_Init
         CMP     a2, #4               ; Codes 4 upwards denote swapped
         MOV     a2, #IIC_Base0 :AND: &FFFF; Start with BSC0
         ADD     a2, a2, #IIC_Base0 :AND: &FFFF0000
-        MOVHS   a2, #IIC_Base1 :AND: &FFFF; If rev code 4 upwards, use BCS1
+        MOVHS   a2, #IIC_Base1 :AND: &FFFF; If rev code 4 upwards, use BSC1
         ADDHS   a2, a2, #IIC_Base1 :AND: &FFFF0000
         STR     a2, IIC_Base         ; Store the choice
-; Set up output pins of BSC0 and BSC1
-; Set GPIO0 to SDA0, GPIO1 to SCL0, GPIO2 to SDA1 and GPIO3 to SCL1
+; Set up pins GPIO0 to SDA0, GPIO1 to SCL0 or
+;             GPIO2 to SDA1, GPIO3 to SCL1
 ; Only adjust the configuration of the pins for the controller we're using -
 ; the other pins/controller might be being used for a different purpose (e.g.
 ; Pi 3, GPIO 0/SDA0 seems related to power control/under-voltage detection)
         LDR     a2, PeriBase
         ADD     a3, a2, #GPIO_Base
-        LDR     a2, [a3, #GPFSel0]   ; Must set GPIO0..3 to alt-f0
-        BICLO   a2, a2, #8_00000077  ; which is binary 100
+        LDR     a2, [a3, #GPFSel0]
+        BICLO   a2, a2, #8_00000077
         BICHS   a2, a2, #8_00007700
-        ORRLO   a2, a2, #8_00000044
+        ORRLO   a2, a2, #8_00000044  ; Set FSEL to ALT0 which is binary 100
         ORRHS   a2, a2, #8_00004400
         STR     a2, [a3, #GPFSel0]
         DoMemBarrier a1              ; Ensure all peripheral registers
 ; Enable the controller
-        BaseAddr a4, a1              ; a4 -> IIC controller 0
+        BaseAddr a4, a1              ; a4 -> IIC controller
         LDR     a1, [a4, #IIC_C]     ; a1 = Control reg's contents
         ORR     a1, a1, #IIC_I2CEN   ; Enable the controller
         STR     a1, [a4, #IIC_C]