Commit 3467df7b authored by ROOL's avatar ROOL 🤖

Report POR flag to the kernel

Detail:
  Look at the reset status register and use the HADPOR flag to influence the OSStartFlag_POR value.
  Fixes problem of OS_Byte 253 always reporting a hard reset, never a power on reset.
Admin:
  Tested on a Pi 2.
  Submission for USB bounty.

Version 0.64. Tagged as 'BCM2835-0_64'
parent e5872c90
/* (0.63)
/* (0.64)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.63
#define Module_MajorVersion_CMHG 0.64
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 25 Oct 2016
#define Module_Date_CMHG 10 Dec 2016
#define Module_MajorVersion "0.63"
#define Module_Version 63
#define Module_MajorVersion "0.64"
#define Module_Version 64
#define Module_MinorVersion ""
#define Module_Date "25 Oct 2016"
#define Module_Date "10 Dec 2016"
#define Module_ApplicationDate "25-Oct-16"
#define Module_ApplicationDate "10-Dec-16"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.63"
#define Module_HelpVersion "0.63 (25 Oct 2016)"
#define Module_LibraryVersionInfo "0:63"
#define Module_FullVersion "0.64"
#define Module_HelpVersion "0.64 (10 Dec 2016)"
#define Module_LibraryVersionInfo "0:64"
......@@ -445,19 +445,34 @@ DMA_CH_Count * 12 ; Was 13, but firmware bug is incorrectly reporting tha
; Message-based parallel host interface
MPHI_Base * &00006000
;
; Power management
PM_Base * &00100000 ; power management
PM_Rstc * &1c ; reset control reg
PM_Rsts * &20 ; reset status reg (?)
PM_Wdog * &24 ; watchdog control reg
PM_Password * &5a000000 ; for writes to be accepted
PM_GNRIC * &00
PM_AUDIO * &04
PM_STATUS * &18
PM_RSTC * &1c ; reset control reg
PM_RSTS * &20 ; reset status reg
PM_WDOG * &24 ; watchdog control reg
; register bits
PM_Wdog_Reset * &00 ; watchdog reset
PM_Password * &5a000000
PM_Wdog_TimeSet * &000fffff
PM_Rst_WCfgClr * &ffffffcf
PM_Rst_WCfgSet * &00000030
PM_Rst_WCfg_FullRst * &00000020
PM_Rst_Reset * &00000102
PM_RSTC_DRCFG_MASK * &00000003
PM_RSTC_WRCFG_MASK * &00000030
PM_RSTC_WRCFG_FULLRST * &00000020
PM_RSTC_SRCFG_MASK * &00000300
PM_RSTC_QRCFG_MASK * &00003000
PM_RSTC_FRCFG_MASK * &00030000
PM_RSTC_HRCFG_MASK * &00300000
PM_RSTS_HADDRQ * 1:SHL:0
PM_RSTS_HADDRF * 1:SHL:1
PM_RSTS_HADDRH * 1:SHL:2
PM_RSTS_HADWRQ * 1:SHL:4
PM_RSTS_HADWRF * 1:SHL:5
PM_RSTS_HADWRH * 1:SHL:6
PM_RSTS_HADSRQ * 1:SHL:8
PM_RSTS_HADSRF * 1:SHL:9
PM_RSTS_HADSRH * 1:SHL:10
PM_RSTS_HADPOR * 1:SHL:12
PM_WDOG_TIME_MASK * &000fffff
;
;
USB_Base * &00980000 ; USB
......
......@@ -437,8 +437,14 @@ clear_lp1
; OS kernel informed of RAM areas
LDR a2, PeriBase
ADD a2, a2, #PM_Base
LDR a2, [a2, #PM_RSTS] ; consider reset status
TST a2, #PM_RSTS_HADPOR
LDR a4,[sp],#4 ;!!! ref from last AddRAM
MOV a1, #OSStartFlag_RAMCleared
ORRNE a1, a1, #OSStartFlag_POR
ADRL a2, HAL_Base + OSROM_HALSize ; a2 -> RISC OS image
ADR a3, HALdescriptor
......@@ -851,14 +857,14 @@ HAL_Reset
LDR a1, PeriBase
ADD a1, a1, #PM_Base
DoMemBarrier a3
LDR a2, [a1, #PM_Rstc]
LDR a2, [a1, #PM_RSTC]
MOV a3, #PM_Password
BIC a2, a2, #PM_Rst_WCfgSet
ORR a2, a2, #PM_Rst_WCfg_FullRst
BIC a2, a2, #PM_RSTC_WRCFG_MASK
ORR a2, a2, #PM_RSTC_WRCFG_FULLRST
ORR a2, a2, a3
ADD a3, a3, #10
STR a3, [a1, #PM_Wdog]
STR a2, [a1, #PM_Rstc]
STR a3, [a1, #PM_WDOG]
STR a2, [a1, #PM_RSTC]
B .
HAL_PhysInfo ROUT
......
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