Commit 2b3d4781 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add workaround for Cortex-A7 errata 814220

Detail:
  hdr/BCM2835 - Errata 814220 states that the Cortex-A7 set/way cache maintenance operations violate the usual operation ordering rules, such that an L2 maintenance operation which is started after an L1 operation may actually complete before it, causing data corruption if the L1 data was to be evicted to the L2 entry. Implement the suggested workaround of performing a DSB when switching cache levels, rather than just at the end of the combined L1+L2 group of operations.
  Also, fix missing 99 label that would have caused a stack imbalance in the unlikely event of encountering a processor with fully coherent caches
Admin:
  Tested on Raspberry Pi 2


Version 0.43. Tagged as 'BCM2835-0_43'
parent 1b785be4
/* (0.42) /* (0.43)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 0.42 #define Module_MajorVersion_CMHG 0.43
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Feb 2015 #define Module_Date_CMHG 07 Feb 2015
#define Module_MajorVersion "0.42" #define Module_MajorVersion "0.43"
#define Module_Version 42 #define Module_Version 43
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "03 Feb 2015" #define Module_Date "07 Feb 2015"
#define Module_ApplicationDate "03-Feb-15" #define Module_ApplicationDate "07-Feb-15"
#define Module_ComponentName "BCM2835" #define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835" #define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.42" #define Module_FullVersion "0.43"
#define Module_HelpVersion "0.42 (03 Feb 2015)" #define Module_HelpVersion "0.43 (07 Feb 2015)"
#define Module_LibraryVersionInfo "0:42" #define Module_LibraryVersionInfo "0:43"
...@@ -331,10 +331,11 @@ $label MRC p15, 1, $clidr, c0, c0, 1 ; read CLIDR ...@@ -331,10 +331,11 @@ $label MRC p15, 1, $clidr, c0, c0, 1 ; read CLIDR
BGE %BT30 BGE %BT30
SUBS $way, $way, #1 SUBS $way, $way, #1
BGE %BT20 BGE %BT20
DSB ; Cortex-A7 errata 814220: DSB required when changing cache levels when using set/way operations. This also counts as our end-of-maintenance DSB.
40 ADD $level, $level, #2 40 ADD $level, $level, #2
CMP $level, $loc CMP $level, $loc
BLT %BT10 BLT %BT10
DSB 99
MEND MEND
MACRO MACRO
......
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