Commit 1b785be4 authored by Ben Avison's avatar Ben Avison
Browse files

Properly supports new board revision scheme for SD source file

Detail:
  Parses the revision ID bitfield for new-style revisions - should provide
  some level of forward compatibility at last. The equivalent code in s.GPIO
  hasn't been tackled yet, mainly because it requires some thought about how
  best to handle the Compute module (given that the daughter card can be
  plugged into any number of devices, each of which will use GPIO differently).
Admin:
  Tested on Compute module and Pi 2 with latest firmware.

Version 0.42. Tagged as 'BCM2835-0_42'
parent 0f6c0f83
/* (0.41)
/* (0.42)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.41
#define Module_MajorVersion_CMHG 0.42
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 02 Feb 2015
#define Module_Date_CMHG 03 Feb 2015
#define Module_MajorVersion "0.41"
#define Module_Version 41
#define Module_MajorVersion "0.42"
#define Module_Version 42
#define Module_MinorVersion ""
#define Module_Date "02 Feb 2015"
#define Module_Date "03 Feb 2015"
#define Module_ApplicationDate "02-Feb-15"
#define Module_ApplicationDate "03-Feb-15"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.41"
#define Module_HelpVersion "0.41 (02 Feb 2015)"
#define Module_LibraryVersionInfo "0:41"
#define Module_FullVersion "0.42"
#define Module_HelpVersion "0.42 (03 Feb 2015)"
#define Module_LibraryVersionInfo "0:42"
......@@ -60,8 +60,28 @@ MIN_SDCLK * 400
BoardRevision_BPlus * &10
BoardRevision_Compute * &11
BoardRevision_APlus * &12
; Starting with the Pi 2, board revisions appear to have changed to a bitfield
; scheme. Any bitfield value will significantly exceed these old "enum" revisions.
; Starting with the Pi 2, board revisions have changed to a bitfield scheme:
BoardRevision_NewScheme * 1 :SHL: 23 ; if set, indicates the following are in use
BoardRevision_Mem_256M * 0 :SHL: 20
BoardRevision_Mem_512M * 1 :SHL: 20
BoardRevision_Mem_1G * 2 :SHL: 20
BoardRevision_Mem_Mask * 7 :SHL: 20
BoardRevision_Manuf_Sony * 0 :SHL: 16
BoardRevision_Manuf_Egoman * 1 :SHL: 16
BoardRevision_Manuf_Embest * 2 :SHL: 16
BoardRevision_Manuf_Embest2 * 4 :SHL: 16
BoardRevision_Manuf_Mask * 15 :SHL: 16
BoardRevision_Proc_2835 * 0 :SHL: 12
BoardRevision_Proc_2836 * 1 :SHL: 12
BoardRevision_Proc_Mask * 15 :SHL: 12
BoardRevision_Model_A * 0 :SHL: 4
BoardRevision_Model_B * 1 :SHL: 4
BoardRevision_Model_APlus * 2 :SHL: 4
BoardRevision_Model_BPlus * 3 :SHL: 4
BoardRevision_Model_B2 * 4 :SHL: 4
BoardRevision_Model_Compute * 6 :SHL: 4
BoardRevision_Model_Mask * 255 :SHL: 4
BoardRevision_Rev_Mask * 15 :SHL: 0
; Base address of controller as an offset from PeriBase
EMMC_Base * &00300000
......@@ -332,9 +352,16 @@ SDIO_InitDevices ROUT
BL memcpy
LDR a3, Board_Revision
BIC a3, a3, #&FF000000 ; mask off overclocking / user bits
TST a3, #BoardRevision_NewScheme
BNE %FT01
CMP a3, #BoardRevision_BPlus
TEQ a3, #BoardRevision_Compute
; So now LO => model A or B, EQ => Compute, HI => A+, B+ or Pi 2
B %FT02
01 AND a3, a3, #BoardRevision_Model_Mask
CMP a3, #BoardRevision_Model_APlus
TEQ a3, #BoardRevision_Model_Compute
02 ; So now LO => model A or B, EQ => Compute, HI => A+, B+ or Pi 2
; Activate
ADRLO a1, Activate_AB
......
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