Commit 0a5cd22b authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

Update GPIO pullup/pulldown code to support Pi4

Detail:
* Fixes register corruption in GPIOPullDirection.
* Pre-seeds the soft copies with the values from the datasheet (so no need for a function
  to read them). This should also help other models of Pi which assumed they were all
  disabled when it seems they are not!
* Reworks the SDIO driver to call through to the GPIO so that its softcopy is kept in
  sync, and so the settings do something on a Pi 4 at all.
Admin:
  Tested on Pi4 and a Pi 3B+.

Version 0.91. Tagged as 'HAL_BCM2835-0_91'
parent 810e6f25
/* (0.90)
/* (0.91)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.90
#define Module_MajorVersion_CMHG 0.91
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 09 Sep 2020
#define Module_Date_CMHG 10 Oct 2020
#define Module_MajorVersion "0.90"
#define Module_Version 90
#define Module_MajorVersion "0.91"
#define Module_Version 91
#define Module_MinorVersion ""
#define Module_Date "09 Sep 2020"
#define Module_Date "10 Oct 2020"
#define Module_ApplicationDate "09-Sep-20"
#define Module_ApplicationDate "10-Oct-20"
#define Module_ComponentName "HAL_BCM2835"
#define Module_FullVersion "0.90"
#define Module_HelpVersion "0.90 (09 Sep 2020)"
#define Module_LibraryVersionInfo "0:90"
#define Module_FullVersion "0.91"
#define Module_HelpVersion "0.91 (10 Oct 2020)"
#define Module_LibraryVersionInfo "0:91"
......@@ -343,9 +343,12 @@ GPIO_InitDevices
MOV a3, #HALDevice_GPIO_Size_1_0
BL memcpy
MOV a2, #0
; 3 2 1 0
; 10987654321098765432109876543210
LDR a2, =2_11001111111111111111111111111111
LDR a3, =2_00000000000000000000000111111111
STR a2, [a1, #WkspPullEnable]
STR a2, [a1, #WkspPullDirection]
STR a3, [a1, #WkspPullDirection]
STR sb, [a1, #WkspCopySB]
ADRL a2, GPIO_Description_0
......@@ -358,13 +361,16 @@ GPIO_InitDevices
; Copy dev struct to WS & fill in the non template items
ADRL a1, GPIO1Device
ADR a2, GPIOTemplate
ADRL a2, GPIOTemplate
MOV a3, #HALDevice_GPIO_Size_1_0
BL memcpy
MOV a2, #0
; 6 5 4 3
; 32109876543210987654321098765432
LDR a2, =2_00000011111111111100111111111111
LDR a3, =2_00000011111111111100000000011100
STR a2, [a1, #WkspPullEnable]
STR a2, [a1, #WkspPullDirection]
STR a3, [a1, #WkspPullDirection]
STR sb, [a1, #WkspCopySB]
ADRL a2, GPIO_Description_1
......@@ -396,6 +402,7 @@ GPIO_InitDevices
CallOS OS_AddDevice ; register device1
]
EXIT
LTORG
GPIO_Activate
MOV a1, #1
......@@ -666,9 +673,9 @@ GPIOPullDirection
ORR a2, a3, a2 ; new soft copy
STR a2, [a1, #WkspPullDirection]
LDR a4, [a1, #WkspPullEnable]
AND a2, a2, a4
AND ip, a2, a4
AND a3, v1, a4
TEQ a2, a3
TEQ ip, a3
MOVEQ a1, v1 ; no enabled sense change
EXIT EQ
......@@ -816,6 +823,9 @@ GPIO_Pull_Common
LDR v1, [a1, #HALDevice_Address]
LDR sb, [a1, #WkspCopySB]
LDR a1, [a1, #HALDevice_GPIONumber]
CPUDetect v2
BHI %FT20
ASSERT GPPUDCK0 + 4 = GPPUDCK1
MOV a4, #GPPUDCK0
ADD v4, a4, a1, LSL #2
......@@ -848,6 +858,36 @@ GPIO_Pull_Common
STR a2, [v1, v4]
MOV a1, #50 ; guess
B HAL_CounterDelay
20
; BCM2838 has different pull control registers
ASSERT GPPUDCT0 + 4 = GPPUDCT1
ASSERT GPPUDCT1 + 4 = GPPUDCT2
ASSERT GPPUDCT2 + 4 = GPPUDCT3
MOV a4, #GPPUDCT0
ADD v4, a4, a1, LSL #3 ; offset of pair of control registers for this port
MOV a1, #1 ; src bit mask
30
MOV a4, #0 ; dst bit number
MOV v2, #0 ; dst
40
TEQ a1, #0
EXIT EQ
MOV ip, #2_00 ; disabled
TST a2, a1
ORRNE ip, ip, #2_10 ; pull down
TSTNE a3, a1
EORNE ip, ip, #2_11 ; convert down to up
ORR v2, v2, ip, LSL a4
ADD a4, a4, #2
MOV a1, a1, LSL #1
TST a4, #&1F
BNE %BT40
DataSyncBarrier ip
STR v2, [v1, v4] ; dump to hardware
ADD v4, v4, #4 ; offset for next 16 bits
DataSyncBarrier ip
B %BT30
; Port wide pin modifier
; Enter with a1 = device pointer
......
......@@ -49,10 +49,6 @@ sb RN 9
; Timings
; How long to wait during GPIO pullup/down register procedure
; This is documented as "150 cycles" but not what these are cycles of!
PUD_DELAY * 150 ; in us - wild guess
; How long to wait for SDCLK to stabilise, in ms
CLOCKSET_TIMEOUT * 20 ; in ms
......@@ -521,42 +517,36 @@ PinMux_SetFunction ROUT
; a1 = GPIO pin
; a2 = pull type
GPIO_SetPull ROUT
Push "v1,lr"
MOV v1, a1
LDR ip, PeriBase
ADD ip, ip, #GPIO_Base
STR a2, [ip, #GPPUPDEN]
MOV a1, #PUD_DELAY
BL HAL_CounterDelay
LDR ip, PeriBase
MOV lr, #1
ADD ip, ip, #GPIO_Base
ADD ip, ip, #GPPUDCK0
AND a1, v1, #&1F
MOV a2, v1, LSR #5
MOV lr, lr, LSL a1
STR lr, [ip, a2, LSL #2]
MOV a1, #PUD_DELAY
BL HAL_CounterDelay
LDR ip, PeriBase
MOV a1, #0
ADD ip, ip, #GPIO_Base
ADD ip, ip, #GPPUDCK0
MOV a2, v1, LSR #5
; Manual recommends unsetting registers in this order, but I'm paranoid about an interrupt going off in between
MRS lr, CPSR
ORR v1, lr, #&C0 ; I and F bits
MSR CPSR_c, v1
STR a1, [ip, #GPPUPDEN - GPPUDCK0]
STR a1, [ip, a2, LSL #2]
MSR CPSR_c, lr
Pull "v1,pc"
Push "v1-v3,lr"
MOV v2, a2
CMP a1, #32 ; Select a port
AND v1, a1, #&1F ; Pin on the port
ADRCCL v3, GPIO0Device
ADRCSL v3, GPIO1Device
TEQ v2, #GPIO_PUD_OFF
BEQ %FT10
; Do the up/down
MOV ip, #1
MOV a2, ip, LSL v1
TEQ v2, #GPIO_PUD_UP
MOVEQ a3, ip, LSL v1
MOVNE a3, #0
LDR ip, [v3, #HALDevice_GPIOPullDirection]
MOV a1, v3
BLX ip
10
; Do the enable/disable
MOV ip, #1
MOV a2, ip, LSL v1
TEQ v2, #GPIO_PUD_OFF
MOVNE a3, ip, LSL v1
MOVEQ a3, #0
LDR ip, [v3, #HALDevice_GPIOPullControl]
MOV a1, v3
BLX ip
Pull "v1-v3,pc"
; a1 = GPIO pin
; a2 = value to set (0 or 1)
......
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