Commit 0821d828 authored by Ben Avison's avatar Ben Avison Committed by ROOL

Peripheral physical addresses have moved again

Also:
* the IO region previously used only for the QA7 extensions now holds a GIC
  as well on Pi 4, so give it a more generic name
* there's a new, second peripheral IO region to map in as well
parent 0b2f7c19
......@@ -87,7 +87,11 @@ JTAG SETL {FALSE}
;ROM_Base * &00000000
IO_Base_BCM2835 * &20000000
IO_Base_BCM2836 * &3F000000 ; it moves in Pi 2
IO_Size * &01000000
IO_Base_BCM2838 * &FE000000 ; and again in Pi 4
IO_Base2_BCM2838 * &FC000000 ; Pi 4 adds a second range of peripherals
IO_Size_BCM2835 * &01000000
IO_Size_BCM2838 * &01800000
IO_Size2_BCM2838 * &02000000
RAM_Base * &00000000 ; try off bottom
Boot_RAM_Base * &00000000
DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes
......@@ -97,12 +101,16 @@ GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coher
GPU_L1L2Cac * &00000000 ; both L1 and L2 cached GPU side
GPU_CacheMask * &c0000000
; Exit CC if ARM11, CS if A7/A53
; Exit CC if ARM11, EQ if A7/A53, HI if A72, CS if A7/A53/A72
MACRO
$label CPUDetect $reg
$label MRC p15, 0, $reg, c0, c0, 0 ; read Main ID Register
AND $reg, $reg, #&FF00
CMP $reg, #&C000 ; xxxxB76x for ARM1176, xxxxC07x for Cortex-A7
; xxxxB76x for ARM1176, xxxxC07x for Cortex-A7, xxxxD03x for Cortex-A53, xxxxD08x for Cortex-A72
UXTH $reg, $reg
MOV $reg, $reg, LSR #4
SUB $reg, $reg, #&C07 :AND: &F
SUBS $reg, $reg, #&C07 :AND: &FF0
TEQNE $reg, #&D03 - &C07
MEND
; Acquire/release the HAL spinlock
......@@ -308,6 +316,8 @@ BoardRevision_Mem_Mask * 7 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_256M * 0 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_512M * 1 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_1G * 2 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_2G * 3 :SHL: BoardRevision_Mem_Shift
BoardRevision_Mem_4G * 4 :SHL: BoardRevision_Mem_Shift
BoardRevision_Manuf_Shift * 16
BoardRevision_Manuf_Mask * 15 :SHL: BoardRevision_Manuf_Shift
BoardRevision_Manuf_Sony * 0 :SHL: BoardRevision_Manuf_Shift
......@@ -321,6 +331,7 @@ BoardRevision_Proc_Mask * 15 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2835 * 0 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2836 * 1 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2837 * 2 :SHL: BoardRevision_Proc_Shift
BoardRevision_Proc_2838 * 3 :SHL: BoardRevision_Proc_Shift
BoardRevision_Model_Shift * 4
BoardRevision_Model_Mask * 255 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_A * 0 :SHL: BoardRevision_Model_Shift
......@@ -336,6 +347,7 @@ BoardRevision_Model_ZeroW * 12 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_B3Plus * 13 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_A3Plus * 14 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_Compute3Plus * 16 :SHL: BoardRevision_Model_Shift
BoardRevision_Model_B4 * 17 :SHL: BoardRevision_Model_Shift
BoardRevision_Rev_Shift * 0
BoardRevision_Rev_Mask * 15 :SHL: BoardRevision_Rev_Shift
......@@ -632,9 +644,16 @@ IIC_DIV * &14 ; Clock Divider
IIC_DEL * &18 ; Data Delay
IIC_CLKT * &1C ; Clock Stretch Timeout
; The peripherals (including the local interrupt controller) introduced with
; the Quad Cortex-A7, and the GIC (in BCM2838) share an IO region.
INT_BASE_BCM2836 * &40000000
INT_BASE_BCM2838 * &FF800000
INT_SIZE * &800000
; When accessing by virtual address, the following are relative to IntBase
; ARM control registers for quad core chips (BCM2836, BCM2837, etc.)
; ref: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
QA7_BASE * &40000000
QA7_CONTROL * &0000
QA7_CORE_TIMER_PRESCALE * &0008
QA7_GPU_INT_ROUTING * &000C
......@@ -695,7 +714,20 @@ QA7_CORE3_MBOX0_RDCLR * &00F0
QA7_CORE3_MBOX1_RDCLR * &00F4
QA7_CORE3_MBOX2_RDCLR * &00F8
QA7_CORE3_MBOX3_RDCLR * &00FC
QA7_SIZE * &40000
; Extra peripheral range added at Pi 4. These are all relative to PeriBase2
; V3D
V3D_Base * &00500000
; PCIe
PCIe_Base * &01500000
; Gigabit Ethernet
GENET_Base * &01580000
; Thermal sensor
Thermal_Base * &015d2200
]
END
......@@ -87,8 +87,9 @@ sb RN 9
^ 0,sb
PeriBase # 4
IntBase # 4
PeriBase2 # 4
IRQ_Base_Address # 4
QA7_Base # 4
ARM_Counter_IO_Address # 4
ARM_Timer_IO_Address # 4
UARTOldModemStatus # 4
......
......@@ -50,7 +50,7 @@ DBell_InitDevices ROUT
MOV a3, #HALDevice_DBell_Size
BL memcpy
ADRL a2, DBellDevice
LDR a1, QA7_Base
LDR a1, IntBase
ADD a1, a1, #QA7_CORE0_MBOX0_RDCLR
STR a1, [a2, #HALDevice_Address]
MOV a1, #0
......
......@@ -85,7 +85,7 @@ QA7_HAL_IRQEnable ROUT
ToggleIRQ
AND a3, a2, #3 ; Extract core number
MOV a2, a2, LSR #2 ; Bit/device number
LDR a1, QA7_Base
LDR a1, IntBase
AcquireSpinlock
ADD pc, pc, a2, LSL #2
NOP
......@@ -264,7 +264,7 @@ QA7_GPU_IRQ_bit * 1<<((iDev_QA7_GPU-iDev_QA7_Base)>>2)
QA7_HAL_IRQSource
DoMemBarrier ip
LDR a2, QA7_Base
LDR a2, IntBase
MRC p15, 0, a1, c0, c0, 5 ; Read MPIDR
AND a3, a1, #3 ; Extract core number
ASSERT QA7_CORE1_IRQ_SOURCE-QA7_CORE0_IRQ_SOURCE = 4
......@@ -306,7 +306,7 @@ QA7_HAL_IRQStatus ROUT
SUBS a3, a1, #iDev_QA7_Base
BLT %FT50
DoMemBarrier ip
LDR a2, QA7_Base
LDR a2, IntBase
AND a1, a3, #3 ; Extract core number
MOV a3, a3, LSR #2 ; Bit/device number
ASSERT QA7_CORE1_IRQ_SOURCE-QA7_CORE0_IRQ_SOURCE = 4
......@@ -393,7 +393,7 @@ HAL_FIQDisable_GPU
MOV pc, lr
QA7_HAL_FIQDisableAll ROUT
LDR a1, QA7_Base
LDR a1, IntBase
MRC p15, 0, a3, c0, c0, 5 ; Read MPIDR
AND a3, a3, #3 ; Extract core number
; Disable PMU FIQ for this core
......@@ -446,7 +446,7 @@ ARM11_HAL_FIQDisableAll
QA7_HAL_FIQSource
DoMemBarrier ip
LDR a2, QA7_Base
LDR a2, IntBase
MRC p15, 0, a1, c0, c0, 5 ; Read MPIDR
AND a3, a1, #3 ; Extract core number
ASSERT QA7_CORE1_FIQ_SOURCE-QA7_CORE0_FIQ_SOURCE = 4
......@@ -478,7 +478,7 @@ QA7_HAL_FIQStatus ROUT
SUBS a3, a1, #iDev_QA7_Base ; For GPU interrupts just skip straight to reading the pending registers (shouldn't really matter whether we own the GPU FIQ or not)
BLT %FT50
DoMemBarrier ip
LDR a2, QA7_Base
LDR a2, IntBase
AND a1, a3, #3 ; Extract core number
MOV a3, a3, LSR #2 ; Bit/device number
ASSERT QA7_CORE1_FIQ_SOURCE-QA7_CORE0_FIQ_SOURCE = 4
......
......@@ -255,8 +255,11 @@ start
STR r4, MMUOffBaseAddr
CPUDetect r4
LDRCC r4,=IO_Base_BCM2835
LDRCS r4,=IO_Base_BCM2836
LDREQ r4,=IO_Base_BCM2836
LDRHI r4,=IO_Base_BCM2838
STR r4,PeriBase
LDRHI r4,=IO_Base2_BCM2838
STRHI r4,PeriBase2
[ HALDebug
mov a1, #0
......@@ -371,7 +374,8 @@ relocate_10
; so that we don't break them when we overwrite the boot stub.
CPUDetect lr
BCC clear_ram
LDR a1, =QA7_BASE
LDREQ a1, =INT_BASE_BCM2836
LDRHI a1, =INT_BASE_BCM2838
MVN a2, #0
STR a2, [a1, #QA7_CORE0_MBOX1_RDCLR] ; Clear our mailboxes
STR a2, [a1, #QA7_CORE0_MBOX2_RDCLR]
......@@ -475,13 +479,17 @@ holding_pattern
AND a1, a1, #3 ; Extract core number (should be 1-3)
[ HALDebug
DSB
LDR a2, =IO_Base_BCM2836+UART_Base
CPUDetect a2
LDREQ a2, =IO_Base_BCM2836+UART_Base
LDRHI a2, =IO_Base_BCM2838+UART_Base
ADD a3, a1, #'0'
STRB a3, [a2, #UARTDR]
]
DSB
; Clear our mailbox register
LDR a2, =QA7_BASE
CPUDetect a2
LDREQ a2, =INT_BASE_BCM2836
LDRHI a2, =INT_BASE_BCM2838
ADD a3, a2, #QA7_CORE0_MBOX0_SET
ADD a3, a3, a1, LSL #2 ; Box to reply to core 0 on
ADD a4, a2, #QA7_CORE0_MBOX3_RDCLR
......@@ -499,7 +507,9 @@ holding_pattern
BEQ %BT10
[ HALDebug
DSB
LDR a2, =IO_Base_BCM2836+UART_Base
CPUDetect a2
LDREQ a2, =IO_Base_BCM2836+UART_Base
LDRHI a2, =IO_Base_BCM2838+UART_Base
ADD a3, a1, #'0'
STRB a3, [a2, #UARTDR]
]
......@@ -710,20 +720,33 @@ HAL_Init
; Map in the A7/A53 control logic
MOV a1, #L1_S
LDR a2, =QA7_BASE
LDR a3, =QA7_SIZE
LDREQ a2, =INT_BASE_BCM2836
LDRHI a2, =INT_BASE_BCM2838
LDR a3, =INT_SIZE
CallOS OS_MapInIO
STR a1, QA7_Base
STR a1, IntBase
LDR a2, =IO_Base_BCM2836
CPUDetect a2
LDREQ a2, =IO_Base_BCM2836
LDRHI a2, =IO_Base_BCM2838
05
; Map in the main IO region
MOVCC a1, #0
MOVCS a1, #L1_S
LDR a3, =IO_Size
LDRLS a3, =IO_Size_BCM2835
LDRHI a3, =IO_Size_BCM2838
CallOS OS_MapInIO
STR a1, PeriBase
; Map in the secondary IO region
CPUDetect a2
BLS %FT06
MOV a1, #L1_S
LDR a2, =IO_Base2_BCM2838
LDR a3, =IO_Size2_BCM2838
CallOS OS_MapInIO
STR a1, PeriBase2
06
[ Debug
MOV a1,#0 ; start the uart ..we use it for debug
BL HAL_UARTStartUp ; restart to capture logical io address
......@@ -954,15 +977,19 @@ HAL_PhysInfo ROUT
; Fill in IO region
CPUDetect v5
SUB a2, a2, #524288-(IO_Base_BCM2835>>13)
ADDCS a2, a2, #(IO_Base_BCM2836-IO_Base_BCM2835)>>13
ADDEQ a2, a2, #(IO_Base_BCM2836-IO_Base_BCM2835)>>13
ADDHI a2, a2, #(IO_Base2_BCM2838-IO_Base_BCM2835)>>13
ORR a1, a1, a1, LSR #1 ; Pattern for IO regions
ORR a3, a3, a3, LSR #1
ORR a4, a4, a4, LSR #1
ORR v3, v3, v3, LSR #1
ADD v5, a2, #IO_Size>>13
ASSERT IO_Base_BCM2836+IO_Size = QA7_BASE
ASSERT QA7_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
ADDCS v5, v5, #QA7_SIZE>>13
ADDLO v5, a2, #IO_Size_BCM2835>>13
ASSERT IO_Base_BCM2836+IO_Size_BCM2835 = INT_BASE_BCM2836
ADDEQ v5, a2, #(IO_Size_BCM2835+INT_SIZE)>>13
ASSERT IO_Base2_BCM2838+IO_Size2_BCM2838 = IO_Base_BCM2838
ASSERT IO_Base_BCM2838+IO_Size_BCM2838 = INT_BASE_BCM2838
ADDHI v5, a2, #(IO_Size2_BCM2838+IO_Size_BCM2838+INT_SIZE)>>13
ASSERT INT_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
20
STMIA a2!, {a1,a3,a4,v3}
CMP a2, v5
......@@ -1014,7 +1041,7 @@ QA7_HAL_CPUNumber
; Out: Indicated core will be booting (undefined if a1 is current core)
; Assume caller has fully flushed the boot code to RAM (no DSB prior to mbox write)
QA7_HAL_SMPStartup
LDR a3, QA7_Base
LDR a3, IntBase
ASSERT QA7_CORE1_MBOX3_SET-QA7_CORE0_MBOX3_SET = 16
ADD a3, a3, a1, LSL #4
STR a2, [a3, #QA7_CORE0_MBOX3_SET]
......
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