Commit 068d02ad authored by Ben Avison's avatar Ben Avison Committed by ROOL

Get IRQs working

Detail:
* For now, this uses the legacy interrupt controller, whose register layout has
  unfortunately changed in some unhelpful ways. There is also a GICv2 in the
  SoC, which we will need to transition across to in order to use some of the
  newer peripherals (including USB3 and gigabit Ethernet).
* This requires a corresponding set of changes to start.elf: substitute all
  three instances of &E30011E7 with &E3001000.
* FIQs are not currently supported, as the legacy interrupt controller has
  changed how these are handled. It seems likely that we'll transition to
  GIC before too long, which means it's not worth bothering to implement them
  for the legacy interrupt controller.
parent 932e3f57
......@@ -506,19 +506,52 @@ IRQ_Base * &0000B200
IRQ_PENDB * &00 ; read: pending basic interrupts (devices 64-95)
IRQ_PEND1 * &04 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31)
IRQ_PEND2 * &08 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63)
IRQ_FIQCTL * &0C ; FIQ control register
; In BCM2838, IRQ_PEND* have shuffled round to match the order of the other registers!
IRQ_PEND1_BCM2838 * &00 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31)
IRQ_PEND2_BCM2838 * &04 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63)
IRQ_PENDB_BCM2838 * &08 ; read: pending basic interrupts (devices 64-95)
IRQ_FIQCTL * &0C ; FIQ control register - not on BCM2838
IRQ_EN1 * &10 ; read: enabled interrupts 1; write: bits to OR into enabled interrupts 1
IRQ_EN2 * &14 ; read: enabled interrupts 2; write: bits to OR into enabled interrupts 2
IRQ_ENB * &18 ; read: enabled basic interrupts; write: bits to OR into enabled basic interrupts
IRQ_DIS1 * &1C ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1
IRQ_DIS2 * &20 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2
IRQ_DISB * &24 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts
; In BCM2838, IRQ_DIS* move along by 4 bytes!
IRQ_DIS1_BCM2838 * &20 ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1
IRQ_DIS2_BCM2838 * &24 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2
IRQ_DISB_BCM2838 * &28 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts
;
; FIQ handling (BCM2838 only)
;
FIQ_Base * &0000B300
FIQ_PEND1 * &00 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31)
FIQ_PEND2 * &04 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63)
FIQ_PENDB * &08 ; read: pending basic interrupts (devices 64-95)
FIQ_EN1 * &10 ; read: enabled interrupts 1; write: bits to OR into enabled interrupts 1
FIQ_EN2 * &14 ; read: enabled interrupts 2; write: bits to OR into enabled interrupts 2
FIQ_ENB * &18 ; read: enabled basic interrupts; write: bits to OR into enabled basic interrupts
FIQ_DIS1 * &20 ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1
FIQ_DIS2 * &24 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2
FIQ_DISB * &28 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts
; Raspberry Pi interrupt sources.
; Because the pending and enable registers are listed in different orders, there are 2 logical ways to map these onto
; device numbers. However, matching the order of the enable registers has the following advantages:
; * the same device numbers can be used in the FIQ control register without modification
; * the GPU timer interrupts end up with the lowest priority - desirable since we run our counter from them
; There are 4 groups of interrupt sources:
; * 64 GPU interrupts. On BCM2835-7, these are mapped to bits in the "1" and "2"
; registers, but some are also mapped into the upper 24 bits of the "base"
; interrupt registers. We don't use the upper bits of the "base" registers
; because masking is only possible in the "1" and "2" registers, because
; IRQ_FIQCTL also (and only) accepts sources in that order, and because it
; keeps the timers with the lowest priority, which is desirable because we run
; our counter from them. BCM2838 has the same interrupt controller block, but
; it is normally disabled in favour of the GICv2, which features additional
; important interrupt sources. Add 64 to the GPU interrupt number to find the
; equivalent GIC interrupt number.
; * 8 ARM interrupts. On BCM2835-7, these are mapped into the bottom 8 bits of
; the "base" interrupt registers. Add 32 to the ARM interrupt number to find
; the equivalent GIC interrupt number.
; * 32 core-specific interrupts managed by the QA7 block in BCM2836-8.
; * (At least) four other banks of 32 GPU interrupts in the GIC in BCM2838.
; devices in register 1 - start at 0
iDev_GPU_Timer0 * 0 ; not on list in datasheet
......@@ -544,19 +577,26 @@ iDev_GPU_VCDMA3 * 19 ; not on list in datasheet
iDev_GPU_DMA4 * 20 ; not on list in datasheet
iDev_GPU_DMA5 * 21 ; not on list in datasheet
iDev_GPU_DMA6 * 22 ; not on list in datasheet
iDev_GPU_DMA7 * 23 ; not on list in datasheet
iDev_GPU_DMA8 * 24 ; not on list in datasheet
iDev_GPU_DMA9 * 25 ; not on list in datasheet
iDev_GPU_DMA10 * 26 ; not on list in datasheet
iDev_GPU_DMA11 * 27 ; not on list in datasheet
iDev_GPU_DMA12 * 28 ; not on list in datasheet
iDev_GPU_AuxInt * 29
iDev_GPU_DMA7 * 23 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA7_8 * 23 ; channels 7 & 8 use shared interrupt on BCM2838
iDev_GPU_DMA8 * 24 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA9_10 * 24 ; channels 9 & 10 use shared interrupt on BCM2838
iDev_GPU_DMA9 * 25 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_0 * 25 ; BCM2838
iDev_GPU_DMA10 * 26 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_1 * 26 ; BCM2838
iDev_GPU_DMA11 * 27 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_2 * 27 ; BCM2838
iDev_GPU_DMA12 * 28 ; not on list in datasheet; BCM2835-7
iDev_GPU_DMA40_3 * 28 ; BCM2838
iDev_GPU_AuxInt * 29 ; shared SPI1, SPI2, UART1
iDev_GPU_ARM * 30 ; not on list in datasheet
iDev_GPU_VPUDMA * 31 ; not on list in datasheet
; devices in register 2 - start at 32
iDev_GPU_HostPort * 32 ; not on list in datasheet
iDev_GPU_VidScale * 33 ; not on list in datasheet
iDev_GPU_CCP2TX * 34 ; not on list in datasheet
iDev_GPU_ArgonLocalIntC * 34 ; BCM2838
iDev_GPU_SDC * 35 ; not on list in datasheet
iDev_GPU_DSI0 * 36 ; not on list in datasheet
iDev_GPU_AVE * 37 ; not on list in datasheet
......@@ -567,24 +607,24 @@ iDev_GPU_HDMI1 * 41 ; not on list in datasheet
iDev_GPU_PixVal1 * 42 ; not on list in datasheet
iDev_GPU_I2CSPISlv * 43
iDev_GPU_DSI1 * 44 ; not on list in datasheet
iDev_GPU_PWA0 * 45
iDev_GPU_PWA1 * 46
iDev_GPU_PWA0 * 45 ; PixelValve on BCM2838
iDev_GPU_PWA1 * 46 ; PixelValve on BCM2838
iDev_GPU_CPR * 47 ; not on list in datasheet
iDev_GPU_SMI * 48
iDev_GPU_SMI * 48 ; also FirmwareKMS
iDev_GPU_GPIO0 * 49
iDev_GPU_GPIO1 * 50
iDev_GPU_GPIO2 * 51
iDev_GPU_GPIO3 * 52
iDev_GPU_I2C * 53
iDev_GPU_SPI * 54
iDev_GPU_I2C * 53 ; shared I2C0-I2C2 on BCM2835-7; shared I2C0-I2C6 on BCM2838
iDev_GPU_SPI * 54 ; SPI0 on BCM2835-7; shared SPI0, SPI3-SPI6 on BCM2838
iDev_GPU_PCM * 55
iDev_GPU_SDIO * 56 ; not on list in datasheet
iDev_GPU_Uart * 57
iDev_GPU_SDIO * 56 ; not on list in datasheet; only controller on BCM235-7; backward-compatible controller on BCM2838
iDev_GPU_Uart * 57 ; UART0 on BCM2835-7; shared UART0, UART2-5 on BCM2838
iDev_GPU_SlimBus * 58 ; not on list in datasheet
iDev_GPU_Vec * 59 ; not on list in datasheet
iDev_GPU_CPG * 60 ; not on list in datasheet
iDev_GPU_RNG * 61 ; not on list in datasheet
iDev_GPU_VCSDIO * 62 ; not on list in datasheet
iDev_GPU_VCSDIO * 62 ; not on list in datasheet; fast controller on BCM2838
iDev_GPU_AVSPMON * 63 ; not on list in datasheet
iDev_ARM_Timer * 64+0
iDev_ARM_Mbx * 64+1
......@@ -594,13 +634,6 @@ iDev_ARM_GPU0Hlt * 64+4
iDev_ARM_GPU1Hlt * 64+5
iDev_ARM_IllegAcs1 * 64+6
iDev_ARM_IllegAcs0 * 64+7
; Notice that bits 8-31 of the pending basic interrupts cannot be masked. This causes the RISC OS kernel problems,
; because the default action for an unhandled interrupt is to mask it, and if masking doesn't work, we end up with an
; infinite loop. You *could* map these device numbers back to bits in the disable interrupts 1/2 registers, but it's
; not a simple mapping and the same bits appear in the pending interrupts 1/2 registers as well, so they're arguably
; not much use. Is the saving of one or two reads of the pending interrupt registers worth the complexity? I don't know.
; It's also worth noting that these device numbers are not valid for use as FIQs. So for now, I recommend you don't use
; these devices - use the equivalents in the GPU interrupt registers instead.
iDev_ARM_MiscGPU1 * 64+8 ; OR of GPU IRQs 0-31 excluding those listed below
iDev_ARM_MiscGPU2 * 64+9 ; OR of GPU IRQs 32-63 excluding those listed below
iDev_ARM_VCJPEG * 64+10 ; copy of GPU IRQ 7
......@@ -640,6 +673,26 @@ iDev_QA7_LocalTimer # 4 ; Can only be assigned to one core (as either IRQ or
iDev_QA7_Max # 0
; GIC interrupt sources
; For now, these are the literal interrupt numbers and haven't had any offsets applied
; TODO: figure out how to combine them into the unified iDev numberspace
iDev_GIC_PMU0 * 16
iDev_GIC_PMU1 * 17
iDev_GIC_PMU2 * 18
iDev_GIC_PMU3 * 19
iDev_GIC_VCUSB * 40 ; additional interrupt for DWC
iDev_GIC_Thermal * 137
iDev_GIC_PCIe0 * 143
iDev_GIC_PCIe1 * 144
iDev_GIC_PCIe2 * 145
iDev_GIC_PCIe3 * 146
iDev_GIC_PCIe4 * 148
iDev_GIC_Genet0 * 157
iDev_GIC_Genet1 * 158
iDev_GIC_XHCI * 176
;IIC0 (BSC0, i.e. Broadcom Serial Controller 0)
IIC_Base0 * &00205000 ; base of IIC0
;IIC1 (BCS1, i.e. Broadcom Serial Controller 1)
......@@ -724,6 +777,63 @@ QA7_CORE3_MBOX1_RDCLR * &00F4
QA7_CORE3_MBOX2_RDCLR * &00F8
QA7_CORE3_MBOX3_RDCLR * &00FC
; GIC (added at Pi 4)
GICD_Base * &00041000
GICD_CTLR * &000
GICD_TYPER * &004
GICD_IIDR * &008
GICD_IGROUPR * &080
GICD_ISENABLER * &100
GICD_ICENABLER * &180
GICD_ISPENDR * &200
GICD_ICPENDR * &280
GICD_ISACTIVER * &300
GICD_ICACTIVER * &380
GICD_IPRIORITYR * &400
GICD_ITARGETSR * &800
GICD_ICFGR * &C00
GICD_PPISR * &D00
GICD_SPISR * &D04
GICD_SGIR * &F00
GICD_CPENDSGIR * &F10
GICD_SPENDSGIR * &F20
GICD_PIDR4 * &FD0
GICD_PIDR5 * &FD4
GICD_PIDR6 * &FD8
GICD_PIDR7 * &FDC
GICD_PIDR0 * &FE0
GICD_PIDR1 * &FE4
GICD_PIDR2 * &FE8
GICD_PIDR3 * &FEC
GICD_CIDR0 * &FF0
GICD_CIDR1 * &FF4
GICD_CIDR2 * &FF8
GICD_CIDR3 * &FFC
GICC_Base * &00042000
GICC_CTLR * &0000
GICC_PMR * &0004
GICC_BPR * &0008
GICC_IAR * &000C
GICC_EOIR * &0010
GICC_RPR * &0014
GICC_HPPIR * &0018
GICC_ABPR * &001C
GICC_AIAR * &0020
GICC_AEOIR * &0024
GICC_AHPPIR * &0028
GICC_APR0 * &00D0
GICC_NSAPR0 * &00E0
GICC_IIDR * &00FC
GICC_DIR * &1000
; The GIC virtual interfaces probably aren't interesting unless you're writing
; a hypervisor.
; Extra peripheral range added at Pi 4. These are all relative to PeriBase2
; V3D
......
......@@ -20,12 +20,14 @@
MEND
MACRO
QA7Entry $name
VarEntry $name
ASSERT (. - $table) / 4 = EntryNo_$name
[ $table_idx == 0
DCD ARM11_$name - $table
|
ELIF $table_idx == 1
DCD QA7_$name - $table
|
DCD VC6_$name - $table
]
MEND
......
......@@ -56,6 +56,20 @@
EXPORT QA7_HAL_IRQSetCores
EXPORT QA7_HAL_IRQGetCores
EXPORT VC6_HAL_IRQEnable
EXPORT VC6_HAL_IRQDisable
EXPORT VC6_HAL_IRQSource
EXPORT VC6_HAL_IRQStatus
EXPORT VC6_HAL_FIQEnable
EXPORT VC6_HAL_FIQDisable
EXPORT VC6_HAL_FIQDisableAll
EXPORT VC6_HAL_FIQSource
EXPORT VC6_HAL_FIQStatus
EXPORT VC6_HAL_IRQMax
EXPORT VC6_HAL_IRQProperties
EXPORT VC6_HAL_IRQSetCores
EXPORT VC6_HAL_IRQGetCores
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
......@@ -76,6 +90,7 @@ Interrupt_Init
MOV pc, lr
VC6_HAL_IRQEnable
QA7_HAL_IRQEnable ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
......@@ -229,6 +244,25 @@ ExitZero
MOV a1, #0
MOV pc, lr
VC6_HAL_IRQDisable ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
SUBS a2, a1, #iDev_QA7_Base
MOVGE a4, #0 ; Signal this is an IRQ disable event
BGE ToggleIRQ
DoMemBarrier ip
LDR ip, IRQ_Base_Address
ADD ip, ip, #IRQ_DIS1_BCM2838
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
LDR a4, [ip, a3, LSL #2] ; get old enable mask
STR a2, [ip, a3, LSL #2] ; disable our bit
AND a1, a2, a4 ; test our bit in old mask
DoMemBarrier ip
MOV pc, lr
QA7_HAL_IRQDisable ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
......@@ -262,6 +296,44 @@ HAL_FIQClear
QA7_GPU_IRQ_bit * 1<<((iDev_QA7_GPU-iDev_QA7_Base)>>2)
VC6_HAL_IRQSource
DoMemBarrier ip
LDR a2, IntBase
MRC p15, 0, a1, c0, c0, 5 ; Read MPIDR
AND a3, a1, #3 ; Extract core number
ASSERT QA7_CORE1_IRQ_SOURCE-QA7_CORE0_IRQ_SOURCE = 4
ADD a2, a2, a3, LSL #2
LDR a2, [a2, #QA7_CORE0_IRQ_SOURCE]
ADD a3, a3, #iDev_QA7_Base
; Prioritise core-specific interrupts over general ones
BIC a1, a2, #QA7_GPU_IRQ_bit
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a3, a1, LSL #2
BPL %FT90
TST a2, #QA7_GPU_IRQ_bit
BEQ %FT90 ; No GPU interrupt, so must be spurious? (a1 already -1)
; Read GPU interrupt source using BCM2838 register mappings
DoMemBarrier ip
LDR a2, IRQ_Base_Address
LDRB a1, [a2, #IRQ_PENDB_BCM2838] ; note, LDRB so we ignore bits 8-31
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_ARM_Timer ; 64
BPL %FT90
LDR a1, [a2, #IRQ_PEND2_BCM2838]
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_GPU_HostPort ; 32
BPL %FT90
LDR a1, [a2, #IRQ_PEND1_BCM2838]
CLZ a1, a1
RSB a1, a1, #31
90
DoMemBarrier ip
MOV pc, lr
QA7_HAL_IRQSource
DoMemBarrier ip
LDR a2, IntBase
......@@ -300,11 +372,30 @@ ARM11_HAL_IRQSource
DoMemBarrier ip
MOV pc, lr
QA7_HAL_IRQStatus ROUT
VC6_HAL_IRQStatus ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
SUBS a3, a1, #iDev_QA7_Base
BGE %FT40
; GPU pending registers now go in device order, so can't reuse ARM11 code
DoMemBarrier ip
LDR ip, IRQ_Base_Address
ASSERT IRQ_PEND1_BCM2838 = 0
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
LDR a4, [ip, a3, LSL #2] ; get pending mask
AND a1, a2, a4 ; test our bit
DoMemBarrier ip
MOV pc, lr
QA7_HAL_IRQStatus
CMP a1, #iDev_QA7_Max
BHS ExitZero
SUBS a3, a1, #iDev_QA7_Base
BLT %FT50
40
DoMemBarrier ip
LDR a2, IntBase
AND a1, a3, #3 ; Extract core number
......@@ -341,6 +432,10 @@ ARM11_HAL_IRQStatus
FIQEnable * 1<<7
FIQSourceMask * &7F
VC6_HAL_FIQEnable ROUT
; TODO
MOV pc,lr
QA7_HAL_FIQEnable ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
......@@ -366,6 +461,10 @@ HAL_FIQEnable_GPU
DoMemBarrier ip
MOV pc, lr
VC6_HAL_FIQDisable ROUT
; TODO
MOV pc, lr
QA7_HAL_FIQDisable ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
......@@ -392,6 +491,10 @@ HAL_FIQDisable_GPU
DoMemBarrier ip
MOV pc, lr
VC6_HAL_FIQDisableAll ROUT
; TODO
MOV pc, lr
QA7_HAL_FIQDisableAll ROUT
LDR a1, IntBase
MRC p15, 0, a3, c0, c0, 5 ; Read MPIDR
......@@ -444,6 +547,11 @@ ARM11_HAL_FIQDisableAll
DoMemBarrier ip
MOV pc, lr
VC6_HAL_FIQSource
; TODO
MOV a1, #0
MOV pc, lr
QA7_HAL_FIQSource
DoMemBarrier ip
LDR a2, IntBase
......@@ -472,6 +580,11 @@ ARM11_HAL_FIQSource
DoMemBarrier ip
MOV pc, lr
VC6_HAL_FIQStatus ROUT
; TODO
MOV a1, #0
MOV pc, lr
QA7_HAL_FIQStatus ROUT
CMP a1, #iDev_QA7_Max
BHS ExitZero
......@@ -509,6 +622,7 @@ ARM11_HAL_IRQMax
MOV a1, #iDev_ARM11_Max
MOV pc, lr
VC6_HAL_IRQMax
QA7_HAL_IRQMax
MOV a1, #iDev_QA7_Max
MOV pc, lr
......@@ -520,6 +634,7 @@ QA7_HAL_IRQMax
; assigned to
; bit 30 = private flag
; bit 31 = interrupt can be routed to multiple cores at once
VC6_HAL_IRQProperties
QA7_HAL_IRQProperties
CMP a1, #iDev_QA7_Max
MOVHS a1, #0
......@@ -548,6 +663,8 @@ ARM11_HAL_IRQProperties
; In: a1 = device number
; a2 = desired core mask
; Out: a1 = actual core mask
VC6_HAL_IRQSetCores
VC6_HAL_IRQGetCores
QA7_HAL_IRQSetCores
QA7_HAL_IRQGetCores ; read-only version of IRQSetCores
CMP a1, #iDev_QA7_Max
......
......@@ -75,6 +75,19 @@
IMPORT QA7_HAL_IRQProperties
IMPORT QA7_HAL_IRQSetCores
IMPORT QA7_HAL_IRQGetCores
IMPORT VC6_HAL_IRQEnable
IMPORT VC6_HAL_IRQDisable
IMPORT VC6_HAL_IRQSource
IMPORT VC6_HAL_IRQStatus
IMPORT VC6_HAL_FIQEnable
IMPORT VC6_HAL_FIQDisable
IMPORT VC6_HAL_FIQDisableAll
IMPORT VC6_HAL_FIQSource
IMPORT VC6_HAL_FIQStatus
IMPORT VC6_HAL_IRQMax
IMPORT VC6_HAL_IRQProperties
IMPORT VC6_HAL_IRQSetCores
IMPORT VC6_HAL_IRQGetCores
IMPORT Timer_Init
IMPORT HAL_Timers
......@@ -466,7 +479,8 @@ clear_lp1
ADRL a2, HAL_Base + OSROM_HALSize ; a2 -> RISC OS image
CPUDetect a3
ADRCCL a3, HALdescriptor
ADRCSL a3, QA7_HALdescriptor
ADREQL a3, QA7_HALdescriptor
ADRHIL a3, VC6_HALdescriptor
CallOSM OS_Start
......@@ -518,9 +532,10 @@ holding_pattern
LTORG
; Generate two HAL descriptors - one for ARM11 based systems and one for A7/A53
; Generate three HAL descriptors - one for ARM11 based systems, one for A7/A53
; and one for A72.
; This allows us to avoid extra overheads in some critical routines
; Entries created using 'QA7Entry' will use either ARM11_$name or QA7_$name
; Entries created using 'VarEntry' will use either ARM11_$name, QA7_$name or VC6_$name
GBLA table_idx
GBLA entries
......@@ -529,12 +544,14 @@ holding_pattern
table_idx SETA 0
WHILE table_idx < 2
WHILE table_idx < 3
[ table_idx == 0
descriptor SETS "HALdescriptor"
|
ELIF table_idx == 1
descriptor SETS "QA7_HALdescriptor"
|
descriptor SETS "VC6_HALdescriptor"
]
table SETS "$descriptor._EntryTable"
......@@ -542,17 +559,17 @@ table SETS "$descriptor._EntryTable"
$table DATA
HALEntry HAL_Init
QA7Entry HAL_IRQEnable
QA7Entry HAL_IRQDisable
VarEntry HAL_IRQEnable
VarEntry HAL_IRQDisable
HALEntry HAL_IRQClear
QA7Entry HAL_IRQSource
QA7Entry HAL_IRQStatus
QA7Entry HAL_FIQEnable
QA7Entry HAL_FIQDisable
QA7Entry HAL_FIQDisableAll
VarEntry HAL_IRQSource
VarEntry HAL_IRQStatus
VarEntry HAL_FIQEnable
VarEntry HAL_FIQDisable
VarEntry HAL_FIQDisableAll
HALEntry HAL_FIQClear
QA7Entry HAL_FIQSource
QA7Entry HAL_FIQStatus
VarEntry HAL_FIQSource
VarEntry HAL_FIQStatus
HALEntry HAL_Timers
HALEntry HAL_TimerDevice
......@@ -600,7 +617,7 @@ $table DATA
NullEntry ; HAL_VideoBufferAlignment
NullEntry ; HAL_VideoOutputFormat
QA7Entry HAL_IRQProperties
VarEntry HAL_IRQProperties
[ table_idx == 0
NullEntry
NullEntry
......@@ -608,11 +625,11 @@ $table DATA
NullEntry
NullEntry
|
QA7Entry HAL_IRQSetCores
QA7Entry HAL_IRQGetCores
QA7Entry HAL_CPUCount
QA7Entry HAL_CPUNumber
QA7Entry HAL_SMPStartup
VarEntry HAL_IRQSetCores
VarEntry HAL_IRQGetCores
VarEntry HAL_CPUCount
VarEntry HAL_CPUNumber
VarEntry HAL_SMPStartup
]
HALEntry HAL_MachineID
......@@ -678,7 +695,7 @@ $table DATA
HALEntry HAL_Reset
QA7Entry HAL_IRQMax
VarEntry HAL_IRQMax
HALEntry HAL_USBControllerInfo
NullEntry ; HAL_USBPortPower
......@@ -1030,11 +1047,13 @@ HAL_InitDevices
LDR pc, [sp], #4
; Out: a1 = number of CPU cores
VC6_HAL_CPUCount
QA7_HAL_CPUCount
MOV a1, #4
MOV pc, lr
; Out: a1 = number of this core
VC6_HAL_CPUNumber
QA7_HAL_CPUNumber
MRC p15, 0, a1, c0, c0, 5
AND a1, a1, #3
......@@ -1044,6 +1063,7 @@ QA7_HAL_CPUNumber
; a2 = boot physical address
; Out: Indicated core will be booting (undefined if a1 is current core)
; Assume caller has fully flushed the boot code to RAM (no DSB prior to mbox write)
VC6_HAL_SMPStartup
QA7_HAL_SMPStartup
LDR a3, IntBase
ASSERT QA7_CORE1_MBOX3_SET-QA7_CORE0_MBOX3_SET = 16
......
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