Commit 059ba08a authored by Ben Avison's avatar Ben Avison
Browse files

Compatibility with latest Pi firmware

Detail:
  * Recent versions of the firmware call the ROM's entry point in HYP mode
    (except for ARM11 boards which don't have it). Detect this eventuality
    and drop into SVC mode safely if so.
  * Whilst testing this fix, I discovered that occasionally, secondary CPUs
    seem to be being woken up, and start executing the ROM entry point also.
    This shouldn't be happening, but for safety's sake, I'm detecting this
    eventuality and putting any secondary CPUs into a sleep loop.
Admin:
  Tested on Pi 1 and 2. Requires HdrSrc 2.56.

Version 0.49. Tagged as 'BCM2835-0_49'
parent e4b2b1fd
/* (0.48)
/* (0.49)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.48
#define Module_MajorVersion_CMHG 0.49
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Oct 2015
#define Module_Date_CMHG 08 Nov 2015
#define Module_MajorVersion "0.48"
#define Module_Version 48
#define Module_MajorVersion "0.49"
#define Module_Version 49
#define Module_MinorVersion ""
#define Module_Date "29 Oct 2015"
#define Module_Date "08 Nov 2015"
#define Module_ApplicationDate "29-Oct-15"
#define Module_ApplicationDate "08-Nov-15"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.48"
#define Module_HelpVersion "0.48 (29 Oct 2015)"
#define Module_LibraryVersionInfo "0:48"
#define Module_FullVersion "0.49"
#define Module_HelpVersion "0.49 (08 Nov 2015)"
#define Module_LibraryVersionInfo "0:49"
......@@ -197,8 +197,34 @@ data_abort
undefined_instr
B .
start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
start
MRC p15, 0, lr, c0, c0, 0 ; read Main ID Register
AND lr, lr, #&FF00
CMP lr, #&C000 ; xxxxB76x for ARM1176, xxxxC07x for Cortex-A7
BCC %F02 ; no MPIDR or HYP mode in ARM1176
; Sometimes a secondary CPU gets here (indicates a bug somewhere)
; Prevent it doing any further damage if so
MRC p15, 0, lr, c0, c0, 5 ; read MPIDR
TST lr, #&FF
01 WFINE
BNE %BT01
; Some versions of the firmware call us in HYP mode, which requires
; a secret handshake to drop into SVC mode
MRS lr, CPSR
AND lr, lr, #M32_bits
TEQ lr, #HYP32_mode
BNE %F02
ADR lr, %F03
MSR SPSR_cxsf, #F32_bit+I32_bit+SVC32_mode
MSR SPSR_x, #A32_bit
MSR elr_hyp, lr
ERET
02
MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
03
ADRL v1, HAL_Base + OSROM_HALSize ; v1 -> RISC OS image
LDR v8, [v1, #OSHdr_Entries]
ADD v8, v8, v1 ; v8 -> RISC OS entry table
......
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