DMA 25.3 KB
Newer Older
Jeffrey Lee's avatar
Jeffrey Lee committed
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
;
; Copyright (c) 2012, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in the
;       documentation and/or other materials provided with the distribution.
;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
;       may be used to endorse or promote products derived from this software
;       without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;

        AREA    |ARM$$code|, CODE, READONLY, PIC

        GET     Hdr:ListOpts
        GET     Hdr:Macros
        GET     Hdr:Proc
        GET     hdr.BCM2835
        GET     hdr.StaticWS
        GET     hdr.DMA

        IMPORT  memcpy

        EXPORT  DMA_InitDevices

        MACRO
$class  HALDeviceField $field, $value
        LCLS    myvalue
      [ "$value" = ""
myvalue SETS    "$field"
      |
myvalue SETS    "$value"
      ]
        ASSERT  . - %A0 = HALDevice_$class$field
     [ ?HALDevice_$class$field = 2
        DCW     $myvalue
   ELIF ?HALDevice_$class$field = 4
        DCD     $myvalue
      |
        %       ?HALDevice_$class$field
      ]
        MEND

         GBLL    DMADebug
DMADebug SETL    {FALSE} :LAND: HALDebug

         GBLL    DMADebug2 ; Controls high-frequency debug output (DMAL_ListTransferProgress)
DMADebug2 SETL    {FALSE} :LAND: DMADebug

      [ DMADebug
        IMPORT  HAL_DebugTXStrInline
        IMPORT  HAL_DebugHexTX4
      ]

        MACRO
        DebugTX $str
      [ DMADebug
        BL      HAL_DebugTXStrInline
        =       "$str", 13, 10, 0
        ALIGN
      ]
        MEND


; Template for DMA controller

DMACTemplate
0
        HALDeviceField Type,               HALDeviceType_SysPeri + HALDeviceSysPeri_DMAC
        HALDeviceField ID,                 HALDeviceID_DMAC_BCM2835
        HALDeviceField Location,           HALDeviceBus_Sys + HALDeviceSysBus_AHB ; Guess
        HALDeviceField Version,            &10000 ; 1.0
        HALDeviceField Description,        DMAC_Description
        HALDeviceField Address,            0 ; filled in later
        HALDeviceField Reserved1,          0
        HALDeviceField Activate,           DMAC_Activate
        HALDeviceField Deactivate,         DMAC_Deactivate
        HALDeviceField Reset,              DMAC_Reset
        HALDeviceField Sleep,              DMAC_Sleep
        HALDeviceField Device,             -1 ; No global IRQ
        HALDeviceField TestIRQ,            0
        HALDeviceField ClearIRQ,           0
        HALDeviceField Reserved2,          0
DMAC    HALDeviceField Features,           DMAC_Features
DMAC    HALDeviceField Enumerate,          DMAC_Enumerate
DMAC    HALDeviceField Allocate,           DMAC_Allocate
DMAC    HALDeviceField Deallocate,         DMAC_Deallocate
DMAC    HALDeviceField TestIRQ2,           0
        ASSERT  . - %A0 = HALDevice_DMAC_Size_0_1

; Template for DMA channels

DMALTemplate
0
        HALDeviceField Type,                 HALDeviceType_SysPeri + HALDeviceSysPeri_DMAL
        HALDeviceField ID,                   HALDeviceID_DMAL_BCM2835
        HALDeviceField Location,             HALDeviceBus_Sys + HALDeviceSysBus_AHB ; Guess
114
        HALDeviceField Version,              &10000 ; 1.0
Jeffrey Lee's avatar
Jeffrey Lee committed
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161
        HALDeviceField Description,          0 ; filled in later
        HALDeviceField Address,              0 ; filled in later
        HALDeviceField Reserved1,            0
        HALDeviceField Activate,             DMAL_Activate
        HALDeviceField Deactivate,           DMAL_Deactivate
        HALDeviceField Reset,                DMAL_Reset
        HALDeviceField Sleep,                DMAL_Sleep
        HALDeviceField Device,               0 ; filled in later
        HALDeviceField TestIRQ,              DMAL_TestIRQ
        HALDeviceField ClearIRQ,             0
        HALDeviceField Reserved2,            0
DMA     HALDeviceField Features,             DMAL_Features
DMA     HALDeviceField Controller,           0 ; filled in later
DMA     HALDeviceField Abort,                DMAL_Abort
DMA     HALDeviceField SetOptions,           DMAL_SetOptions
DMA     HALDeviceField SetListTransfer,      DMAL_SetListTransfer
DMA     HALDeviceField ListTransferProgress, DMAL_ListTransferProgress
DMA     HALDeviceField ListTransferStatus,   DMAL_ListTransferStatus
DMA     HALDeviceField CurtailListTransfer,  DMAL_CurtailListTransfer
        ASSERT  . - %A0 = HALDevice_DMAL_Size

DMAC_Description
        = "BCM2835 DMA controller", 0

DMAL_Description
        = "BCM2835 DMA channel ", 0, " (lite)", 0

DMAL_IRQs
        DCB     iDev_GPU_DMA0
        DCB     iDev_GPU_DMA1
        DCB     iDev_GPU_VCDMA2
        DCB     iDev_GPU_VCDMA3
        DCB     iDev_GPU_DMA4
        DCB     iDev_GPU_DMA5
        DCB     iDev_GPU_DMA6
        DCB     iDev_GPU_DMA7
        DCB     iDev_GPU_DMA8
        DCB     iDev_GPU_DMA9
        DCB     iDev_GPU_DMA10
        DCB     iDev_GPU_DMA11
        DCB     iDev_GPU_DMA12

        ALIGN

        ; Initialise our HAL devices
DMA_InitDevices ROUT
        Entry   "v1-v5"
162
        LDR     v5, ARM_DMAChannels
Jeffrey Lee's avatar
Jeffrey Lee committed
163
      [ DMADebug
164
        MOV     a1, v5
Jeffrey Lee's avatar
Jeffrey Lee committed
165 166 167 168
        BL      HAL_DebugHexTX4
        DebugTX "GetDMAChannels response"
      ]
        LDR     a1, =(1<<DMA_CH_Count)-1
169 170
        ANDS    v5, v5, a1 ; Mask with the list of channels that we know how to use
        EXIT    EQ ; Exit if none available (may have been claimed by video)
Jeffrey Lee's avatar
Jeffrey Lee committed
171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481
        STR     v5, DMAFreeChannels
        ; Create DMA controller device
        ADR     a1, DMAController
        ADR     a2, DMACTemplate
        MOV     a3, #HALDevice_DMAC_Size_0_1
        BL      memcpy
        LDR     v4, PeriBase
        ADD     v4, v4, #DMA_Base
        STR     v4, DMAController+HALDevice_Address
        ; Register controller device
        MOV     a1, #0
        ADR     a2, DMAController
        MOV     lr, pc
        LDR     pc, OSentries+4*OS_AddDevice
        ; Create devices for each channel
        MOV     v1, #0
        ADRL    v2, DMAChannelList
        ADRL    v3, DMAChannels
10
        ; Are we allowed to use this channel?
        MOV     a1, #1
        TST     v5, a1, LSL v1
        BEQ     %FT40
      [ DMADebug
        MOV     a1, v1
        BL      HAL_DebugHexTX4
        MOV     a1, v3
        BL      HAL_DebugHexTX4
        DebugTX "Create channel"
      ]
        STR     v3, [v2], #4
        MOV     a1, v3
        ADR     a2, DMALTemplate
        MOV     a3, #HALDevice_DMAL_Size
        BL      memcpy
        MOV     a1, v3
        ADR     a2, DMAL_IRQs
        LDRB    a2, [a2, v1]
        STR     a2, [a1, #HALDevice_Device]
        STR     v4, [a1, #HALDevice_Address]
        ADR     a2, DMACDesc
        STR     a2, [a1, #HALDevice_Description]
        ADRL    a3, DMAL_Description
20
        LDRB    a4, [a3], #1
        CMP     a4, #0
        STRNEB  a4, [a2], #1
        BNE     %BT20
        CMP     v1, #10
        MOVGE   ip, #'1'
        STRGEB  ip, [a2], #1
        ADDLT   a4, v1, #'0'
        ADDGE   a4, v1, #'0'-10
        STRB    a4, [a2], #1
        MOV     a4, #1
        MOV     a4, a4, LSL v1
        STR     a4, DMACChanMask
        ANDS    a4, a4, #DMA_CH_is_lite :AND: ((1<<DMA_CH_Count)-1)
30
        LDRNEB  a4, [a3], #1
        CMPNE   a4, #0
        STRB    a4, [a2], #1
        BNE     %BT30
        ADR     a2, DMAController
        STR     a2, [a1, #HALDevice_DMAController]
        STR     sb, DMACWorkspace
        ; Make sure DMA channel is idle
        MOV     a1, v3
        BL      DMAL_Abort
        MOV     a1, #0
        MOV     a2, v3
        MOV     lr, pc
        LDR     pc, OSentries+4*OS_AddDevice
40
        ADD     v1, v1, #1
        ADD     v3, v3, #DMAC_DeviceSize
        CMP     v1, #DMA_CH_Count
        ADD     v4, v4, #DMA_CH_STRIDE
        BLT     %BT10
        ; Work out how many channels we added
        ADRL    v3, DMAChannelList
        SUB     v2, v2, v3
        MOV     v2, v2, LSR #2
        STR     v2, DMANumChannels
        DebugTX "DMA_InitDevices done"
        EXIT

; DMA controller device
; ---------------------

        ; TODO?
DMAC_Activate
        MOV     a1, #1
DMAC_Deactivate
DMAC_Reset
        MOV     pc, lr

        ; TODO?
DMAC_Sleep
        MOV     a1, #0
        MOV     pc, lr

DMAC_Features
        MOV     a1, #0
        MOV     pc, lr

DMAC_Enumerate
        LDR     a2, [a1, #DMANumChannels-DMAController]
        ADD     a1, a1, #DMAChannelList-DMAController
        MOV     pc, lr

DMAC_Allocate   ROUT
        ; a2 = peripheral/DREQ
        ; Note that this will end up favouring the lite channels over the full ones!
        ; We could potentially return different channels depending on what peripheral we're after
        Entry
        MRS     lr, CPSR
        ORR     a4, lr, #I32_bit
        MSR     CPSR_c, a4
        LDR     a3, [a1, #DMAFreeChannels-DMAController]!
        CLZ     a4, a3
        RSBS    a4, a4, #31
        MOVLT   a1, #0 ; No controllers left
        BLT     %FT10
        MOV     ip, #1
        BIC     a3, a3, ip, LSL a4
        STR     a3, [a1], #DMAChannels-DMAFreeChannels
        LDR     ip, =DMAC_DeviceSize
        MLA     a1, ip, a4, a1 ; Compute device address (can't use DMAChannelList since we might have gaps in which channels are available to us)
        STR     a2, DMACDREQ
10
        MSR     CPSR_c, lr
      [ DMADebug
        TEQ     a1, #0
        BEQ     %FT20
        Push    "sb,lr"
        LDR     sb, DMACWorkspace
        BL      HAL_DebugHexTX4
        DebugTX "DMAC_Allocate"
        Pull    "sb,lr"
20
      ]
        EXIT

DMAC_Deallocate ROUT
        ; a2 = peripheral/DREQ
        ; a3 = channel ptr
        Entry
        MRS     lr, CPSR
        ORR     a4, lr, #I32_bit
        MSR     CPSR_c, a4
        LDR     a2, [a1, #DMAFreeChannels-DMAController]!
        LDR     a4, [a3, #:INDEX:DMACChanMask]
        ORR     a2, a2, a4
        STR     a2, [a1]
        MSR     CPSR_c, lr
        EXIT

; DMA channel device
; ------------------

DMAL_Activate   ROUT
      [ DMADebug
        Entry   "sb"
        LDR     sb, DMACWorkspace
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_Activate"
      ]
        LDR     a2, [a1, #HALDevice_Address]
        MRS     a4, CPSR
        ORR     ip, a4, #I32_bit
        MSR     CPSR_c, ip
        DoMemBarrier ip
        ; Start/resume current transfer
        LDR     a3, [a2, #DMACH_CS]
        ORR     a3, a3, #DMA_CS_ACTIVE
        STR     a3, [a2, #DMACH_CS]
        DoMemBarrier ip
        MSR     CPSR_c, a4
      [ DMADebug
        EXIT
      |
        MOV     pc, lr
      ]

DMAL_Deactivate ROUT
        Entry   "sb"
        LDR     sb, DMACWorkspace
        LDR     a3, [a1, #HALDevice_Address]
        MRS     a4, CPSR
        ORR     lr, a4, #I32_bit
        MSR     CPSR_c, lr
      [ DMADebug
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_Deactivate"
      ]
        DoMemBarrier lr
        ; Pause current transfer
        LDR     a2, [a3, #DMACH_CS]
        BIC     ip, a2, #DMA_CS_ACTIVE
        STR     ip, [a3, #DMACH_CS]
      [ DMADebug
        Push    "a1"
        MOV     a1, a2
        BL      HAL_DebugHexTX4
        Pull    "a1"
      ]
        ; Wait
05
        LDR     ip, [a3, #DMACH_CS]
      [ DMADebug
        Push    "a1"
        MOV     a1, ip
        BL      HAL_DebugHexTX4
        Pull    "a1"
      ]
        EOR     ip, ip, #DMA_CS_ACTIVE
        TST     ip, #DMA_CS_PAUSED+DMA_CS_ACTIVE
        BEQ     %BT05
        ; Clear any errors
        MOV     ip, #DMA_DEBUG_READ_ERROR+DMA_DEBUG_FIFO_ERROR+DMA_DEBUG_READ_LAST_NOT_SET_ERROR
        STR     ip, [a3, #DMACH_DEBUG]
        DoMemBarrier lr
        DebugTX "done"
        MSR     CPSR_c, a4
        EXIT

DMAL_Abort
DMAL_Reset
        ROUT
        Entry   "sb"
        LDR     sb, DMACWorkspace
        LDR     a3, [a1, #HALDevice_Address]
        MRS     a4, CPSR
        ORR     lr, a4, #I32_bit
        MSR     CPSR_c, lr
      [ DMADebug
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_Abort/DMAL_Reset"
      ]
        DoMemBarrier lr
        ; Pause current transfer
        LDR     a2, [a3, #DMACH_CS]
        BIC     ip, a2, #DMA_CS_ACTIVE
        STR     ip, [a3, #DMACH_CS]
      [ DMADebug
        Push    "a1"
        MOV     a1, a2
        BL      HAL_DebugHexTX4
        Pull    "a1"
      ]
        ; Wait
05
        LDR     ip, [a3, #DMACH_CS]
      [ DMADebug
        Push    "a1"
        MOV     a1, ip
        BL      HAL_DebugHexTX4
        Pull    "a1"
      ]
        EOR     ip, ip, #DMA_CS_ACTIVE
        TST     ip, #DMA_CS_PAUSED+DMA_CS_ACTIVE
        BEQ     %BT05
        ; Break control block chain
        MOV     lr, #0
        STR     lr, [a3, #DMACH_NEXTCONBK]
        ; Abort current block (and load the next, i.e. none)
        MOV     a2, #DMA_CS_ABORT+DMA_CS_ACTIVE
        STR     lr, [a3, #DMACH_CS]
        ; Wait for idle
10
        LDR     lr, [a3, #DMACH_CS]
      [ DMADebug
        Push    "a1,lr"
        MOV     a1, lr
        BL      HAL_DebugHexTX4
        Pull    "a1,lr"
      ]
        TST     lr, #DMA_CS_ACTIVE
        BNE     %BT10
        DoMemBarrier lr
        ; Reset progress vars
        MOV     a2, #0
        STR     a2, DMACLastProgress
        STR     a2, DMACLastCONBLK_AD
        STR     a2, DMACLastTXFR_LEN
        DebugTX "done"
        MSR     CPSR_c, a4
        EXIT

DMAL_Sleep
        ; Not much we can do here. We could toggle power, but it looks like power is meant to be handled by the VideoCore.
        MOV     a1, #0
        MOV     pc, lr

DMAL_TestIRQ
        ; Even though we aren't using a shared IRQ, we must still provide this entry to keep DMAManager happy
        MOV     a1, #1
        MOV     pc, lr

DMAL_Features
        ; is this a lite or a full channel?
        LDR     a2, DMACChanMask
        TST     a2, #DMA_CH_is_lite :AND: ((1<<DMA_CH_Count)-1)
        ADREQ   a1, features_full
        ADRNE   a1, features_lite
        MOV     pc, lr

numcontrolblocks    * 128 ; 128 blocks = 4K of RAM for blocks, 512K transfer length if non-contiguous physical pages

features_full
482
        DCD     DMAFeaturesFlag_NoInitIRQ ; Features
Jeffrey Lee's avatar
Jeffrey Lee committed
483 484 485 486 487 488
        DCD     DMACB_SIZE * numcontrolblocks ; BlockSize
        DCD     DMACB_ALIGN ; BlockAlign
        DCD     0 ; BlockBound
        DCD     numcontrolblocks ; MaxTransfers
        DCD     &ffffffff ; TransferLimit
        DCD     0 ; TransferBound
489
        ASSERT  (. - features_full) = DMAFeaturesBlockSize
Jeffrey Lee's avatar
Jeffrey Lee committed
490 491

features_lite
492
        DCD     DMAFeaturesFlag_NoInitIRQ ; Features
Jeffrey Lee's avatar
Jeffrey Lee committed
493 494 495 496 497 498
        DCD     DMACB_SIZE * numcontrolblocks ; BlockSize
        DCD     DMACB_ALIGN ; BlockAlign
        DCD     0 ; BlockBound
        DCD     numcontrolblocks ; MaxTransfers
        DCD     &ffff ; TransferLimit
        DCD     0 ; TransferBound
499
        ASSERT  (. - features_lite) = DMAFeaturesBlockSize
Jeffrey Lee's avatar
Jeffrey Lee committed
500 501 502 503

DMAL_SetOptions
        ; Just remember these for later
        STR     a2, DMACOptions
504 505
        BIC     a3, a3, #&ff000000
        ORR     a3, a3, #&7e000000 ; ARM periph addr -> VC bus periph addr
Jeffrey Lee's avatar
Jeffrey Lee committed
506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793
        STR     a3, DMACPeriAddress
        MOV     pc, lr

DMAL_SetListTransfer ROUT
        ; TODO - need to deal with non-infinite circular transfers
        ; a1 = HAL device
        ; a2 = ARM phys addr of scatter list
        ; a3 = log addr of scatter list
        ; a4 = number of entries in scatter list
        ; [sp, #0] = byte length of xfer, or 0 for infinite
        Entry   "v1-v4,sb"
        ; scatter list is a list of (addr, len) pairs
        ; Needs expanding to a list of DMA control blocks
        ; To avoid overwriting the list as we expand it, we'll have to work backwards
        LDR     sb, DMACWorkspace
      [ DMADebug
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_SetListTransfer"
        Push    "a1,a4"
        MOV     a1, a2
        BL      HAL_DebugHexTX4
        MOV     a1, a3
        BL      HAL_DebugHexTX4
        MOV     a1, a4
        BL      HAL_DebugHexTX4
        LDR     a1, [sp, #8*4]
        BL      HAL_DebugHexTX4
        DebugTX
        ; Dump out the scatter list
        MOV     v1, a4, LSL #1
        MOV     v2, a3
01
        MOV     a1, v2
        BL      HAL_DebugHexTX4
        LDR     a1, [v2], #4
        BL      HAL_DebugHexTX4
        DebugTX
        SUBS    v1, v1, #1
        BNE     %BT01
        Pull    "a1"
      ]
        LDR     v4, FB_CacheMode
        ADD     a2, a2, v4 ; ARM phys addr -> DMA phys addr
        SUB     v3, a3, a2
        STR     v3, DMACCBOffset
        ADD     v3, a3, a4, LSL #3 ; (addr, len) pair for current block
        LDR     v2, DMACOptions
        SUB     a4, a4, #1
        ASSERT  DMACB_SIZE = 32
        ADD     a3, a3, a4, LSL #5 ; log addr of current block
        ADD     v1, a2, a4, LSL #5 ; DMA phys addr of current block
        TST     v2, #DMASetOptionsFlag_Circular
        MOVEQ   a2, #0 ; value for DMACB_NEXTCONBK
        LDR     lr, DMACPeriAddress
10
        LDMDB   v3!, {a4, ip}
        ADD     a4, a4, v4
        STR     ip, [a3, #DMACB_TXFR_LEN]
        TST     v2, #DMASetOptionsFlag_Write
        STRNE   lr, [a3, #DMACB_DEST_AD]
        STRNE   a4, [a3, #DMACB_SOURCE_AD]
        STREQ   a4, [a3, #DMACB_DEST_AD]
        STREQ   lr, [a3, #DMACB_SOURCE_AD]
        STR     a2, [a3, #DMACB_NEXTCONBK]
        ASSERT  ?DMACB_RESERVED = 8
        MOV     a2, #0
        STR     a2, [a3, #DMACB_RESERVED]
        STR     a2, [a3, #DMACB_RESERVED+4]
        STR     a2, [a3, #DMACB_STRIDE]
        ; Calculate TI field
        LDR     a2, DMACDREQ
        MOV     a2, a2, LSL #DMA_TI_PERMAP_SHIFT
        TST     v2, #DMASetOptionsFlag_Write
        ORRNE   a2, a2, #DMA_TI_SRC_INC+DMA_TI_DEST_DREQ+DMA_TI_WAIT_RESP
        ORREQ   a2, a2, #DMA_TI_DEST_INC+DMA_TI_SRC_DREQ
        ORR     a2, a2, #DMA_TI_INTEN ; TODO - DMAManager should really tell us whether it wants per-CB IRQs or not
        ; TODO - 128bit reads/writes
        ; TODO - bursts
        TEQ     v3, a3
        ASSERT  DMACB_TI = 0
        STR     a2, [a3], #-DMACB_SIZE
        MOVNE   a2, v1
        SUBNE   v1, v1, #DMACB_SIZE
        BNE     %BT10
      [ DMADebug
        ; Dump out the CB list
        Push    "a1,v1-v2"
        LDR     v2, [sp, #12] ; Grab original a4 (still stashed from earlier debug)
        MOV     v2, v2, LSL #3 ; *8
11
        MOV     a1, v1 ; display VC DMA addr
        BL      HAL_DebugHexTX4
        LDR     a1, [v3], #4 ; fetch from ARM addr
        BL      HAL_DebugHexTX4
        DebugTX
        ADD     v1, v1, #4
        SUBS    v2, v2, #1
        BNE     %BT11
        Pull    "a1,v1-v2,lr" ; junk stashed a4 into lr
      ]
        ; Reset our progress values
        STR     ip, DMACLastTXFR_LEN
        STR     v1, DMACLastCONBLK_AD
        MOV     ip, #0
        STR     ip, DMACLastProgress
        LDR     a2, [a1, #HALDevice_Address]
        DebugTX "Configure transfer"
        MRS     a4, CPSR
        ORR     lr, a4, #I32_bit
        MSR     CPSR_c, lr
        DoMemBarrier lr
        ; Reset channel
        MOV     lr, #DMA_CS_RESET
        STR     lr, [a2, #DMACH_CS]
20
        LDR     lr, [a2, #DMACH_CS]
        TST     lr, #DMA_CS_RESET
        BNE     %BT20
        ; Set list start
        STR     v1, [a2, #DMACH_CONBLK_AD]
        LDR     ip, =DMA_CS_WAIT_FOR_OUTSTANDING_WRITES+(4<<DMA_CS_PRIORITY_SHIFT)+(7<<DMA_CS_PANIC_PRIORITY_SHIFT)
        ; Map the 0-7 DMA speed to an AXI priority (0-15)
        ; For now just add 4
        ; For the panic priority, we'll add 7
        ; (Note these offset have been added to ip above)
        AND     v2, v2, #DMASetOptionsMask_Speed
        ADD     ip, ip, v2, LSL #DMA_CS_PRIORITY_SHIFT-DMASetOptionsShift_Speed
        ADD     ip, ip, v2, LSL #DMA_CS_PANIC_PRIORITY_SHIFT-DMASetOptionsShift_Speed
        STR     ip, [a2, #DMACH_CS]
        DoMemBarrier lr
        DebugTX "done"
        MSR     CPSR_c, a4
        EXIT

DMAL_ListTransferProgress ROUT
      [ DMADebug2
        Entry   "v1-v5,sb"
        LDR     sb, DMACWorkspace
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_ListTransferProgress"
      |
        Entry   "v1-v5"
      ]
        LDR     a2, [a1, #HALDevice_Address]
        MRS     a4, CPSR
        ORR     lr, a4, #I32_bit
        MSR     CPSR_c, lr
        DoMemBarrier lr
        ; Pause current transfer
        LDR     a3, [a2, #DMACH_CS]
        BIC     ip, a3, #DMA_CS_ACTIVE
        STR     ip, [a2, #DMACH_CS]
        ; Wait
05
        LDR     ip, [a2, #DMACH_CS]
        EOR     ip, ip, #DMA_CS_ACTIVE
        TST     ip, #DMA_CS_PAUSED+DMA_CS_ACTIVE
        BEQ     %BT05
        ; Get status
        LDR     v1, [a2, #DMACH_CONBLK_AD]
        LDR     v2, [a2, #DMACH_TXFR_LEN]
        ; Resume
        STR     a3, [a2, #DMACH_CS]
        DoMemBarrier lr
        ; Now get our last status
        LDR     v3, DMACLastProgress
        LDR     v4, DMACLastCONBLK_AD
        LDR     v5, DMACLastTXFR_LEN
        LDR     lr, DMACCBOffset
        ; Walk the control block list until we find the current block
        TEQ     v4, #0
        BEQ     %FT30 ; No transfer active!
        TEQ     v1, v4
        BEQ     %FT20
10
        ADD     v3, v3, v5
        ADD     v4, v4, lr
        LDR     v4, [v4, #DMACB_NEXTCONBK]
        TEQ     v4, #0
        ADDNE   ip, v4, lr
        LDRNE   v5, [ip, #DMACB_TXFR_LEN]
        MOVEQ   v5, #0
        BEQ     %FT30
        TEQ     v1, v4
        BNE     %BT10
        ; We've found the right block. Clamp value of TXFR_LEN read from controller, just in case something's gone wrong
        CMP     v2, v5
        MOVHI   v2, v5
20
        ; Work out how much of this block has been transferred
        SUBS    ip, v5, v2
        BLO     %BT10 ; must be a circular transfer which has wrapped completely since we last checked up on it
        ADD     v3, v3, ip
        MOV     v5, v2
30
        ; Update status
        STR     v3, DMACLastProgress
        STR     v4, DMACLastCONBLK_AD
        STR     v5, DMACLastTXFR_LEN
        MSR     CPSR_c, a4
        MOV     a1, v3
      [ DMADebug2
        BL      HAL_DebugHexTX4
        DebugTX
      ]
        EXIT

DMAL_ListTransferStatus ROUT
        ; Check error flags
        ; All the error flags in the controller pertain to reads, so depending on whether this is a device -> memory or memory -> device transfer we'll set the appropriate flag on exit
        LDR     a2, [a1, #HALDevice_Address]
        DoMemBarrier a4
        LDR     ip, [a2, #DMACH_DEBUG]
        DoMemBarrier a4
        TST     ip, #DMA_DEBUG_READ_ERROR+DMA_DEBUG_FIFO_ERROR+DMA_DEBUG_READ_LAST_NOT_SET_ERROR
        MOVEQ   a1, #0
        MOVEQ   pc, lr
        LDR     a3, DMACOptions
        TST     a3, #DMASetOptionsFlag_Write
        MOVNE   a1, #DMAListTransferStatusFlag_MemoryError
        MOVEQ   a1, #DMAListTransferStatusFlag_DeviceError
        MOV     pc, lr

DMAL_CurtailListTransfer ROUT
        ; TODO - This approach of breaking the chain won't work properly if we've got a circular transfer, and we're asked to transfer more than the loop length
      [ DMADebug
        Entry   "v1-v5,sb"
        LDR     sb, DMACWorkspace
        BL      HAL_DebugHexTX4
        DebugTX "DMAL_CurtailListTransfer"
      |
        Entry   "v1-v5"
      ]
        MOV     v4, a2
        LDR     a2, [a1, #HALDevice_Address]
        MRS     a4, CPSR
        ORR     lr, a4, #I32_bit
        MSR     CPSR_c, lr
        DoMemBarrier lr
        ; Pause current transfer
        LDR     a3, [a2, #DMACH_CS]
        BIC     ip, a3, #DMA_CS_ACTIVE
        STR     ip, [a2, #DMACH_CS]
        ; Wait
05
        LDR     ip, [a2, #DMACH_CS]
        EOR     ip, ip, #DMA_CS_ACTIVE
        TST     ip, #DMA_CS_PAUSED+DMA_CS_ACTIVE
        BEQ     %BT05
        ; Get status
        LDR     v1, [a2, #DMACH_CONBLK_AD]
        LDR     v2, [a2, #DMACH_TXFR_LEN]
        ; Walk the transfer list until v4 bytes have been counted
        MOV     v3, #0
        TEQ     v1, #0
        BEQ     %FT20
        LDR     v5, DMACCBOffset
        ADD     v3, v3, v2 ; We can't easily stop the transfer that's in progress
10
        ; Load up the details of the next block
        ADD     v1, v1, v5
        LDR     v1, [v1, #DMACB_NEXTCONBK]
        TEQ     v1, #0
        BEQ     %FT20
        ADD     ip, v1, v5
        LDR     v2, [ip, #DMACB_TXFR_LEN]
        ; Should we stop in this block?
        SUBS    lr, v4, v3
        MOVLT   lr, #0
        CMP     v2, lr
        BHI     %BT10
        STR     lr, [ip, #DMACB_TXFR_LEN] ; Clamp block length. TODO - Round to transfer unit size
        ADD     v3, v3, lr
        MOV     lr, #0
        STR     lr, [ip, #DMACB_NEXTCONBK] ; Break chain
20
        ; Resume transfer
        STR     a3, [a2, #DMACH_CS]
        DoMemBarrier lr
        MSR     CPSR_c, a4
        MOV     a1, v3
      [ DMADebug
        BL      HAL_DebugHexTX4
        DebugTX
      ]
        EXIT

        END