Commit fe5706c2 authored by Ben Avison's avatar Ben Avison
Browse files

First bits of DMA support: reads bus master information from the HAL and uses...

First bits of DMA support: reads bus master information from the HAL and uses it to create a set of DMA "HAL" devices for use by the DMA Manager.

Also responds to Service_ModulePostInit for the DMA Manager to reregister
(currently only the floppy) DMA channel(s).

Version 3.34. Not tagged
parent d980237a
......@@ -14,3 +14,4 @@
|
Dir <Obey$Dir>
amu_machine clean
stripdepnd
| Copyright 2003 Tematic Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine export
......@@ -10,5 +10,6 @@ NewTransferCode SETL {TRUE}
FloppyPodule SETL {FALSE}
FloppyPCI SETL :LNOT:FloppyPodule
UseDiscOp64 SETL {TRUE}
IDEDMA SETL {TRUE}
END
......@@ -27,5 +27,6 @@ test_version SETL {FALSE}
GBLL FloppyPodule
GBLL FloppyPCI
GBLL UseDiscOp64
GBLL IDEDMA
END
......@@ -14,10 +14,10 @@
Module_MajorVersion SETS "3.34"
Module_Version SETA 334
Module_MinorVersion SETS ""
Module_Date SETS "17 Jan 2003"
Module_ApplicationDate SETS "17-Jan-03"
Module_Date SETS "28 Jan 2003"
Module_ApplicationDate SETS "28-Jan-03"
Module_ComponentName SETS "ADFS"
Module_ComponentPath SETS "RiscOS/Sources/FileSys/ADFS/ADFS"
Module_FullVersion SETS "3.34"
Module_HelpVersion SETS "3.34 (17 Jan 2003)"
Module_HelpVersion SETS "3.34 (28 Jan 2003)"
END
......@@ -6,18 +6,18 @@
*/
#define Module_MajorVersion_CMHG 3.34
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 17 Jan 2003
#define Module_Date_CMHG 28 Jan 2003
#define Module_MajorVersion "3.34"
#define Module_Version 334
#define Module_MinorVersion ""
#define Module_Date "17 Jan 2003"
#define Module_Date "28 Jan 2003"
#define Module_ApplicationDate "17-Jan-03"
#define Module_ApplicationDate "28-Jan-03"
#define Module_ComponentName "ADFS"
#define Module_ComponentPath "RiscOS/Sources/FileSys/ADFS/ADFS"
#define Module_FullVersion "3.34"
#define Module_HelpVersion "3.34 (17 Jan 2003)"
#define Module_HelpVersion "3.34 (28 Jan 2003)"
#define Module_LibraryVersionInfo "3:34"
......@@ -52,6 +52,7 @@ ARM810support SETL {FALSE}
GET Hdr:PCI
GET Hdr:Podule
GET Hdr:DMA
GET Hdr:DMADevice
GET s.NewBits
GET s.ADFSMacros
......@@ -75,6 +76,9 @@ ARM810support SETL {FALSE}
GET s.TokenHelp
GET s.ADFS50
GET s.MFormat
[ IDEDMA
GET s.BusMaster
]
GET s.ADFS_SA
......
......@@ -251,18 +251,36 @@ WinInit ROUT
BVS %FT80 ; branch if error
[ HAL
Push "R9,R12"
SUB SP,SP,#32
[ IDEDMA
SUB SP,SP,#4*4
MOV R2,#4*4
MOV R0,#-1
MOV R1,SP
MOV R8,#0
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
MOV R6,#0
CMPVC R0,#4*4
SETV LO
ADD SP,SP,#4
Pull "R0-R2"
BLVC CreateBusMaster
STR R6,WinIDEDMADeviceHandle
SUB SP,SP,#12*4
MOV R2,#12*4
|
SUB SP,SP,#8*4
MOV R2,#8*4
]
MOV R0,#0
MOV R1,SP
MOV R2,#32
MOV R8,#0
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
Pull "R2-R8,R14"
Pull "R9,R12"
BVS %FT05
CMP R0,#32
CMP R0,#8*4
BLO %FT05
ADR R9,WinIDEHardware
......@@ -284,6 +302,12 @@ WinInit ROUT
MOV R14,#0
STRB R14,[R9,#WinIDEBusNo]
[ IDEDMA
MOV R1,R0
]
MOV R0,#0
BL WinIDESetDefaultTimings
TEQ R3,#0
BLNE WinClaimIDEIRQs
BVS %FT80
......@@ -291,22 +315,39 @@ WinInit ROUT
MOV R0,#0 ; -SRST IEN
STRB R0,[R4,#:INDEX:IDERegDevCtrl]
[ IDEDMA
CMP R1,#12*4
LDRHS R0,[SP,#3*4]
CMPHS R0,#-1
MOVEQ R0,#1
SWIEQ XDMA_AllocateLogicalChannels
MOV R3,R0
Pull "R0-R2" ; R5 already set up
ADD SP,SP,#4
LDR R6,WinIDEDMADeviceHandle
CMP R1,#12*4
BLHS AddBusMasterChannel
]
[ TwinIDEHardware
Push "R9,R12"
SUB SP,SP,#32
[ IDEDMA
SUB SP,SP,#12*4
MOV R2,#12*4
|
SUB SP,SP,#8*4
MOV R2,#8*4
]
MOV R0,#1
MOV R1,SP
MOV R2,#32
MOV R8,#0
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
Pull "R2-R8,R14"
Pull "R9,R12"
BVS %FT05
CMP R0,#32
BLO %FT05
ADD R9,R9,#SzWinIDEHardware
ADR R9,WinIDEHardware + SzWinIDEHardware
STR R2,[R9,#WinIDEHWFlags]
STR R3,[R9,#WinIDEPtr]
STR R4,[R9,#WinIDECtrlPtr]
......@@ -325,12 +366,11 @@ WinInit ROUT
MOV R14,#1
STRB R14,[R9,#WinIDEBusNo]
MOV R0,#0
BL WinIDESetDefaultTimings
[ TwinIDEHardware
[ IDEDMA
MOV R1,R0
]
MOV R0,#2
BL WinIDESetDefaultTimings
]
TEQ R3,#0
BLNE WinClaimIDEIRQs
......@@ -338,7 +378,25 @@ WinInit ROUT
MOV R0,#0 ; -SRST IEN
STRB R0,[R4,#:INDEX:IDERegDevCtrl]
[ IDEDMA
CMP R1,#12*4
LDRHS R0,[SP,#3*4]
CMPHS R0,#-1
MOVEQ R0,#1
SWIEQ XDMA_AllocateLogicalChannels
MOV R3,R0
Pull "R0-R2" ; R5 already set up
ADD SP,SP,#4
LDR R6,WinIDEDMADeviceHandle
CMP R1,#12*4
BLHS AddBusMasterChannel
]
]
[ IDEDMA
TEQ R6,#0
BLNE RegisterBusMaster
]
[ :LNOT:AutoDetectIDE
LDRB R4,WinIDEDrives ; needed later
......@@ -696,6 +754,15 @@ WinDie ROUT
BL WinReleaseIDEIRQs ; (R9->R0,V)
]
[ IDEDMA
; deregister DMA devices (if registered)
Push "R6"
LDR R6,WinIDEDMADeviceHandle
TEQ R6,#0
BLNE DeleteBusMaster
Pull "R6"
]
; release TickerV (if owned)
BL WinReleaseTickerV ; (->R0,V)
......
......@@ -643,18 +643,8 @@ FlpReset ROUT
baddr R4, FlpDMASync
ADR R5, FlpDMAHandlers
STMIA R5, {R0-R4}
MOV R0, #0
LDR R1, =&101
MOV R2, #0
MOV R3, #1
ADR R4, FlpDMAHandlers
MOV R5, SB
SWI XDMA_RegisterChannel
BL FlpRegisterDMAChannel
Pull "R3-R5"
MOVVS R0, #-1
STR R0, FlpDMAHandle
MOV R0, #-1
STR R0, FlpDMATag
]
; Initialize the hardware
......@@ -745,6 +735,40 @@ FlpReset1772
LTORG
[ FloppyPCI
;-----------------------------------------------------------------------;
; FlpRegisterDMAChannel ;
; Invoked when the module receives a post soft reset service call.;
; Claims any vectors needed since these will have been destroyed ;
; by the reset. ;
; ;
; Input: ;
; None ;
; ;
; Output: ;
; None ;
; ;
; Modifies: ;
; R0-R5 ;
;_______________________________________________________________________;
;
FlpRegisterDMAChannel
Push "LR"
MOV R0, #0
LDR R1, =&101
MOV R2, #0
MOV R3, #1
ADR R4, FlpDMAHandlers
MOV R5, SB
SWI XDMA_RegisterChannel
MOVVS R0, #-1
STR R0, FlpDMAHandle
MOV R0, #-1
STR R0, FlpDMATag
Pull "PC"
]
;-----------------------------------------------------------------------;
; FlpBuildDCB ;
; Builds a disk control block for the specified operation ;
......
......@@ -504,6 +504,9 @@ ServiceTable
& ServiceEntry2 - org
& Service_Reset
& Service_Portable
[ FloppyPCI :LOR: IDEDMA
& Service_ModulePostInit
]
& Service_ADFSPoduleIDEDying
& 0
......@@ -521,6 +524,9 @@ ServiceEntry ROUT
TEQS R1,#Service_Reset ; Post reset service call?
TEQNES R1,#Service_Portable ; Portable service?
[ FloppyPCI :LOR: IDEDMA
TEQNES R1,#Service_ModulePostInit ; DMA manager starting?
]
LDRNE LR,=Service_ADFSPoduleIDEDying ; IDE podule dying?
TEQNES R1,LR
Pull "PC",NE ; if no, return
......@@ -537,6 +543,11 @@ ServiceEntry3
TEQS R1,#Service_Portable ; Portable service?
BEQ ServicePortablePower ; Yes then jump
[ FloppyPCI :LOR: IDEDMA
TEQS R1,#Service_ModulePostInit ; Module starting?
BEQ ServiceModulePostInit ; Yes then jump
]
TEQS R1,#Service_Reset ; reset?
Pull "LR",NE ; else IDEPoduleDying
BNE WinIDEPoduleDying
......@@ -547,6 +558,30 @@ ServiceEntry3
BL WinReset ; Iniz winchester drivers
Pull "PC" ; Restore caller's regs/flags and return
[ FloppyPCI :LOR: IDEDMA
; Direct-call re-registration
;
ServiceModulePostInit ROUT
Push "R0-R5"
ADR R0,DMAManagerTitle
01 LDRB R1,[R0],#1
LDRB LR,[R2],#1
TEQ R1,#0
TEQEQ LR,#0
BEQ %FT02 ; String match
TEQ R1,LR
BEQ %BT01
Pull "R0-R5,PC" ; Not a match
02
[ FloppyPCI
BL FlpRegisterDMAChannel
]
Pull "R0-R5,PC"
DMAManagerTitle = "DMAManager", 0
ALIGN
]
; Portable power control
;
[ IDEPower
......
; Copyright 2003 Tematic Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;>BusMaster
SUBT OS_Hardware devices for Bus Master IDE function
; DMA controller device
^ HALDevice_DMAC_Size
Ctrlr_Channels # 4 ; number of associated channels
Ctrlr_LogicalTable # 4 * 2 ; array of logical channel numbers
Ctrlr_PhysicalTable # 4 * 2 ; array of pointers to channel devices
CtrlrSize * :INDEX: @
; DMA channel device
^ HALDevice_DMAL_Size, a1
Chan_Registers # 4 ; as passed to AddBusMasterChannel
Chan_ProgLength # 4 ; total length programmed
Chan_DoneLength # 4 ; length successfully transferred
Chan_CmdSoftCopy # 1 ; soft copy of command register
Chan_ErrorFlags # 1 ; DMAListTransferStatus flags
AlignSpace
ChanSize * :INDEX: @
; Bus master register block
BM_Command * 0
BM_Status * 2
BM_PRDTab * 4
; Register bits
BMCommand_Direction * 1:SHL:3
BMCommand_Enable * 1:SHL:0
BMStatus_SimplexOnly * 1:SHL:7
BMStatus_Dr1DMA * 1:SHL:6
BMStatus_Dr0DMA * 1:SHL:5
BMStatus_Interrupt * 1:SHL:2
BMStatus_Error * 1:SHL:1
BMStatus_Active * 1:SHL:0
BMPRDTab_EOT * 1:SHL:31
CreateBusMaster
;
; Entry:
; R0 = 16-bit ID field for device, allocated from the DMA controller range
; R1 = location bitfield for device
; R2 -> statically held string description of DMA controller device
; (eg "Acer M1535+ super I/O chip IDE controller bus master")
; Exit:
; VS: R0 -> error block, R6 preserved
; VC: R0 corrupt, R6 = handle to pass to other routines
; other registers preserved
;
; This must be called before other routines in this file. It creates the structures
; for the controller device in an RMA block.
;
Entry "r1-r3"
MOV r1, r0, LSL #16
MOV r0, #ModHandReason_Claim
MOV r3, #CtrlrSize
SWI XOS_Module
EXIT VS
MOV r6, r2
ORR r0, r1, #HALDeviceType_SysPeri
ORR r0, r0, #HALDeviceSysPeri_DMAC
LDMIA sp, {r1,r3} ; Location / Description
MOV r2, #0 ; Version
STMIA r6!, {r0-r3}
MOV r0, #0 ; Address
MOV r1, #0
MOV r3, #0
STMIA r6!, {r0-r3}
ADR r0, Controller_Activate
ADR r1, Controller_Deactivate
ADR r2, Controller_Reset
ADR r3, Controller_Sleep
STMIA r6!, {r0-r3}
MOV r0, #-1 ; Device
MOV r1, #0 ; TestIRQ
MOV r2, #0
MOV r3, #0
STMIA r6!, {r0-r3}
ADR r0, Controller_Features
ADR r1, Controller_Enumerate
ADR r2, Controller_Allocate
ADR r3, Controller_Deallocate
STMIA r6!, {r0-r3}
ASSERT HALDevice_DMAC_Size = 4*4*5
MOV r0, #0 ; Ctrlr_Channels
STR r0, [r6]
SUB r6, r6, #HALDevice_DMAC_Size
EXIT
AddBusMasterChannel
;
; Entry:
; R0 = 16-bit ID field for device, allocated from the DMA channel (list-type) range
; R1 = location bitfield for device
; R2 -> statically held string description of DMA channel device
; (eg "Acer M1535+ IDE interface bus master primary channel")
; R3 = logical DMA channel number to assign to device
; R5 = base address of bus master register block
; R6 = controller device to assign channel to (as returned from CreateBusMaster)
;
; Exit:
; VS: R0 -> error block
; VC: R0 corrupt
; other registers preserved
;
; This creates an RMA block for the channel device, and registers it with OS_Hardware.
; Up to two channels can currently be added per controller.
;
Entry "r1-r3,r8"
MOV r1, r0, LSL #16
MOV r0, #ModHandReason_Claim
MOV r3, #ChanSize
SWI XOS_Module
EXIT VS
MOV lr, r2
ORR r0, r1, #HALDeviceType_SysPeri :OR: HALDeviceSysPeri_DMAL
LDMIA sp, {r1,r3} ; Location / Description
MOV r2, #0 ; Version
STMIA lr!, {r0-r3}
MOV r0, #0 ; Address
MOV r1, #0
MOV r3, #0
STMIA lr!, {r0-r3}
ADR r0, Channel_Activate
ADR r1, Channel_Deactivate
ADR r2, Channel_Reset
ADR r3, Channel_Sleep
STMIA lr!, {r0-r3}
MOV r0, #-1 ; Device
MOV r1, #0 ; TestIRQ
MOV r2, #0
MOV r3, #0
STMIA lr!, {r0-r3}
ADR r0, Channel_Features
MOV r1, r6
ADR r2, Channel_Abort
ADR r3, Channel_SetOptions
STMIA lr!, {r0-r3}
ADR r0, Channel_SetListTransfer
ADR r1, Channel_ListTransferProgress
ADR r2, Channel_ListTransferStatus
ADR r3, Channel_CurtailListTransfer
STMIA lr!, {r0-r3,r5} ; Chan_Registers too
ASSERT HALDevice_DMAL_Size = 4*4*6
; Register device
SUB r2, lr, #HALDevice_DMAL_Size + 4*1
MOV r0, r2
MOV r8, #2
SWI XOS_Hardware
BVS %FT90
; Add to controller's list of channels
LDR lr, [r6, #Ctrlr_Channels]
LDR r0, [sp, #4*2]
ADD r6, r6, #Ctrlr_LogicalTable
STR r0, [r6, lr, LSL #2]
ADD r6, r6, #Ctrlr_PhysicalTable - Ctrlr_LogicalTable
STR r2, [r6, lr, LSL #2]
SUB r6, r6, #Ctrlr_PhysicalTable
ADD lr, lr, #1
STR lr, [r6, #Ctrlr_Channels]
EXIT
90 MOV r8, r0
MOV r0, #ModHandReason_Free
SWI XOS_Module
MOV r0, r8
SETV
EXIT
RegisterBusMaster
;
; Entry:
; R6 = handle returned from CreateBusMaster
;
; Exit:
; VS: R0 -> error block
; VC: R0 corrupt
; other registers preserved
;
; This must be called when all channels have been added using AddBusMasterChannel.
; It registers the DMA controller device with OS_Hardware.
;
Entry "r8"
MOV r0, r6
MOV r8, #2
SWI XOS_Hardware
EXIT
DeleteBusMaster
;
; Entry:
; R6 = handle returned from CreateBusMaster
; Exit:
; VS: R0 -> error block
; VC: R0 corrupt, R6 = 0
; other registers preserved
;
; This deregisters all channel and controller devices with OS_Hardware, then frees
; their respective RMA blocks.
;
Entry "r1-r2,r8"
; Deregister the controller first -
; this should error if any of the channels are in use
MOV r0, r6
MOV r8, #3
SWI XOS_Hardware
EXIT VS
LDR r1, [r6, #Ctrlr_Channels]
ADD r6, r6, #Ctrlr_PhysicalTable
TEQ r1, #0
BEQ %FT20
10 LDR r2, [r6, r1, LSL #2]
MOV r0, r2
SWI XOS_Hardware
MOV r0, #ModHandReason_Free
SWI XOS_Module
SUBS r1, r1, #1
BNE %BT10
20 SUB r6, r6, #Ctrlr_PhysicalTable
MOV r0, #ModHandReason_Free
MOV r2, r6
SWI XOS_Module
MOV r6, #0
CLRV
EXIT