Commit 6f1f3934 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Reinstate floppies on IOMD platform

ADFS.s:
  Remove redundant header file.
Adfs05.s/Adfs15.s:
  Group the options a bit more simply, use {TRUE} and {FALSE}.
Adfs12.s/BusMaster.s/IDEDetect.s:
  Use defines instead of magic numbers.
Adfs17.s:
  Organise the offsets from the floppy controller to cover both PCI and IO based controllers.
  Only do the dummy read from the PBI on Tungsten.
Adfs18.s:
  Implement the FIQ equivalent of the 'FlpUseVerify' command switch, modern controllers (!) have a built in verify rather than using a sector read, but the verify command has no data phase and the FIQ handler was sitting waiting for a sector that never arrives.
  Rationalise FlpDRQmask and FlpDRQmaskbit.
Adfs19:
  Rationalise the calls to OS_Hardware by rejigging the assembly time switches.
  Reinstate the non HAL version of IRQ enable for reference.
  On RPCEmu 0.8.8 and 0.8.9 the emulator hangs during the four set of DCB's used to autodetect the drive (Recalibrate/Seek/Seek/Sense) which seems to be due to the way the emulator splits CPU time to floppy emulation time, to avoid this we wait 128us (real time) which is enough emulated time for the controller to have changed state. You probably just want to *CONFIGURE FLOPPIES 0 though.

Tested om A7000, ARM610, StrongARM manipulating a veriety of disc densities for read and write. Also ran the "Test/TestADFS" test program.
RPCEmu 0.8.8 and 0.8.9 boots still, but no attempt has been made to use emulated floppies.

Version 3.46. Tagged as 'ADFS-3_46'
parent e7c1bd3c
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "3.45"
Module_Version SETA 345
Module_MajorVersion SETS "3.46"
Module_Version SETA 346
Module_MinorVersion SETS ""
Module_Date SETS "21 Oct 2012"
Module_ApplicationDate SETS "21-Oct-12"
Module_ComponentName SETS "ADFS"
Module_ComponentPath SETS "castle/RiscOS/Sources/FileSys/ADFS/ADFS"
Module_FullVersion SETS "3.45"
Module_HelpVersion SETS "3.45 (21 Oct 2012)"
Module_FullVersion SETS "3.46"
Module_HelpVersion SETS "3.46 (21 Oct 2012)"
END
/* (3.45)
/* (3.46)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 3.45
#define Module_MajorVersion_CMHG 3.46
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 21 Oct 2012
#define Module_MajorVersion "3.45"
#define Module_Version 345
#define Module_MajorVersion "3.46"
#define Module_Version 346
#define Module_MinorVersion ""
#define Module_Date "21 Oct 2012"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "ADFS"
#define Module_ComponentPath "castle/RiscOS/Sources/FileSys/ADFS/ADFS"
#define Module_FullVersion "3.45"
#define Module_HelpVersion "3.45 (21 Oct 2012)"
#define Module_LibraryVersionInfo "3:45"
#define Module_FullVersion "3.46"
#define Module_HelpVersion "3.46 (21 Oct 2012)"
#define Module_LibraryVersionInfo "3:46"
......@@ -57,7 +57,6 @@ StrongARM SETL {TRUE}
GET Hdr:NewErrors
GET Hdr:Portable
GET Hdr:Proc
GET Hdr:CPU.ARM600
GET Hdr:HALEntries
GET Hdr:PCI
GET Hdr:Podule
......
......@@ -39,45 +39,38 @@
; +++++++++++++++++++++++ For Tube work: ++++++++++++++++++++++++++++++++++++++
GBLS GetAroundBleedingAAsmYetAgain
GetAroundBleedingAAsmYetAgain SETS "; No debug required"
[ Dev
[ Debug
GetAroundBleedingAAsmYetAgain SETS " GET Hdr:Debug"
|
GetAroundBleedingAAsmYetAgain SETS " ! 0, ""No debug required"""
]
]
$GetAroundBleedingAAsmYetAgain
[ Dev
[ Debug
GBLS GetHdrDebug
[ Dev :LAND: Debug
GetHdrDebug SETS "GET Hdr:Debug"
|
GetHdrDebug SETS "; Nothing"
]
$GetHdrDebug
[ Dev :LAND: Debug
; Set to true for debugging through the tube
Host_Debug SETL T
Host_Debug SETL {FALSE}
; Set to true to robustify debugging in IRQ mode
Debug_MaybeIRQ SETL T
]
]
Debug_MaybeIRQ SETL {TRUE}
]
GBLS GetHostFS
[ Dev
[ Debug :LAND: Host_Debug
GetHostFS SETS "GET Hdr:HostFS"
|
GetHostFS SETS "; Nothing"
]
|
GetHostFS SETS "; Nothing"
]
$GetHostFS
[ Dev :LAND: Debug
InsertDebugRoutines
]
GBLS Host_Inclusion
Host_Inclusion SETS ""
[ Dev
[ Debug
[ Host_Debug
Host_Inclusion SETS " GET Hdr:HostFS"
|
Host_Inclusion SETS " ! 0, ""Host debug excluded"""
]
]
]
$Host_Inclusion
[ Dev
[ Debug
InsertDebugRoutines
]
]
; Example tube debug calls:
;
; DSTRING r1, "Failed on reading:",cc
......
......@@ -268,7 +268,7 @@ WinInit ROUT
MOV R2,#4*4
MOV R0,#-1
MOV R1,SP
MOV R8,#0
MOV R8,#OSHW_CallHAL
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
MOV R6,#0
......@@ -287,7 +287,7 @@ WinInit ROUT
]
MOV R0,#0
MOV R1,SP
MOV R8,#0
MOV R8,#OSHW_CallHAL
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
Pull "R2-R8,R14"
......@@ -364,7 +364,7 @@ WinInit ROUT
]
MOV R0,#1
MOV R1,SP
MOV R8,#0
MOV R8,#OSHW_CallHAL
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
Pull "R2-R8,R14"
......@@ -483,7 +483,7 @@ WinInit ROUT
SUB SP,SP,#32
MOV R0,SP
MOV R1,#32
MOV R8,#0
MOV R8,#OSHW_CallHAL
MOV R9,#EntryNo_HAL_ATAControllerInfo
SWI XOS_Hardware
Pull "R2-R8,R14"
......
......@@ -61,12 +61,12 @@
; StrongARM changes for modifying code
;
GBLL FlpMultiFS
FlpMultiFS SETL T ; Include MultiFS code
FlpMultiFS SETL {TRUE} ; Include MultiFS code
MACRO
MACRO
FIQOFF $lab
= ($lab.Fiq-(FiqHandlers)) :SHR: 2
MEND
DCD ($lab.Fiq-(FiqHandlers)) :SHR: 2
MEND
FiqHandlers ;table of offsets of start of FIQ handlers
FIQOFF Verify
......
......@@ -47,6 +47,11 @@ FlpUseFIFO SETL :LNOT:FloppyPCI ; T to use FIFO in the SMC '665
GBLL FlpUseVerify
FlpUseVerify SETL {TRUE} ; T to use Verify command in '665
GBLL FlpMediaCheck
FlpMediaCheck SETL {FALSE} ; T to check density from disc/drive
GBLL FlpFlushPBI ; A dummy flush as XScale 80321 queues PBI writes
FlpFlushPBI SETL FloppyPodule :LOR: FloppyPCI
;-----------------------------------------------------------------------;
; This file provides routines to control the '765 FDC and the disk ;
......@@ -85,16 +90,11 @@ FlpUseVerify SETL {TRUE} ; T to use Verify command in '665
; '765 Hardware Definitions
;--------------------------
;
; [ Prototype
;CnTbase * &3350000 ; Base address of 82C710
; |
;CnTbase * &3010000 ; Base address of 82C710 = PC/AT I/O 000H
; ]
;FlpBase * CnTbase + (&3F0 *4) ; Base address of '765 registers
;FlpDACK * CnTbase + &2000 ; Base address of '765 DMA ACK space
;FlpDACK_TC * CnTbase + &1A000 ; '765 DMA ACK with TC (to terminate DMA)
FlpDACK_TC_Offset * &18000
FlpDACK_Offset * &02000 ; From SuperIO controller base
FlpDACK_TC_Offset * &18000 ; From FlpDACK
FlpHiDensity bit 2 ; Density i/p in IoControl
......@@ -102,8 +102,7 @@ FlpHiDensity bit 2 ; Density i/p in IoControl
FlpFintr * 23 ; Device number for '765 IRQ
FlpIndex * 2 ; Device number for Index pulse IRQ
|
FlpDRQmask * 1 ; '765 DRQ FIQ mask for IOC
FlpDRQmaskbit * 0
FlpDRQmaskbit * 0 ; '765 DRQ FIQ mask for IOC
[ FloppyPodule
FlpFintr * 13
FlpIndex * 13
......@@ -120,7 +119,7 @@ FlpReg_Spacing SETA 1
FlpReg_Spacing SETA 4
]
; FDC registers, offset from FlpBase (word alignment)
; FDC registers, offset from FlpBase
;
FlpStatusA * 0 *FlpReg_Spacing ; R/O Status reg A (PS/2 only)
FlpStatusB * 1 *FlpReg_Spacing ; R/O Status reg A (PS/2 only)
......@@ -586,7 +585,7 @@ FlpGetDskChng ROUT
;
FlpMediaID ROUT
[ HAL
; This wasn't implemented in IOMD anyway
; This bit always read as 1 in IOMD anyway
MOV R0, #FlpHiDensity
|
MOV R0, #IoChip ; R0-> IOC base
......@@ -647,20 +646,20 @@ FlpIndexIRQ ROUT
SUB R1, R1, #&800000
01 MOV R0, #bit2
STRB R0, [R1, #4]
[ {TRUE}
[ FlpFlushPBI
LDRB R0, [R1, #4] ; for safety - 80321 gets a bit
TST R0, #bit2 ; ahead of itself
BNE %BT01
]
]
|
ASSERT FlpIndex < 8
01 MOV R0, #1:SHL:FlpIndex
STRB R0, [R3, #IOCIRQCLRA] ; Clear edge triggered interrupt
[ {TRUE}
[ FlpFlushPBI
LDRB R0, [R3, #IOCIRQREQA] ; for safety - 80321 gets a bit
TST R0, #1:SHL:FlpIndex ; ahead of itself
BNE %BT01
]
]
]
; Enable IRQ's, SVC mode
......
......@@ -52,9 +52,6 @@
;
Adfs18Ed * 10 ; Edition number
GBLL FlpMediaCheck
FlpMediaCheck SETL {FALSE} ; T to check density from disc/drive
;-----------------------------------------------------------------------;
; This file provides the support routines for the Disk Control Block ;
; (DCB) messaging system. The following routines are included: ;
......@@ -204,11 +201,6 @@ FlpMessage ROUT
SlowDownFactor * 10
]
; Dummy read for 80321 PBI, which is accessed through PCI, and needs
; a read to flush out writes
GBLL DummyReadFudge
DummyReadFudge SETL FloppyPodule
[ FloppyPCI
FlpDMAEnable
FlpDMADisable
......@@ -286,10 +278,16 @@ FlpVerifyFIQ ROUT
20
LDR lr, %BT11
]
[ FlpUseVerify
MOV R12, #0 ; We should never get here
ADD R9, R13, #FlpDACK_TC_Offset
LDRB R9, [R9] ; Try a terminal count? Can't hurt!
|
LDRB R9, [R13]
SUB R12, R12, #1
SUBS R11, R11, #1
ADDEQ R13, R13, #FlpDACK_TC_Offset
]
retfiq
DCD 1 ; Where FlpDCBbuffer will be put
DCD 0 ; End of FIQ routine
......@@ -678,9 +676,9 @@ FlpWriteNonScatter ROUT
]
[ FlpUseFIFO
STRB R9, [R13]
[ DummyReadFudge
[ FlpFlushPBI
LDRB R9, [R13, #4]
]
]
SUBS R11, R11, #1
ADDEQ R13, R13, #FlpDACK_TC_Offset
SUBS R12, R12, #1
......@@ -689,9 +687,9 @@ FlpWriteNonScatter ROUT
retfiq
|
STRB R9, [R13]
[ DummyReadFudge
[ FlpFlushPBI
LDRB R9, [R13, #4]
]
]
SUBS R10, R10, #1
ADDEQ R13, R13, #FlpDACK_TC_Offset
LDRGE R9, [R8], #1
......@@ -763,9 +761,9 @@ FlpWriteFIQ_FG ROUT
]
[ FlpUseFIFO
STRB R9, [R13]
[ DummyReadFudge
[ FlpFlushPBI
LDRB R9, [R13, #4]
]
]
SUBS R11, R11, #1
ADDEQ R13, R13, #FlpDACK_TC_Offset
SUBS R12, R12, #1
......@@ -782,9 +780,9 @@ FlpWriteFIQ_FG ROUT
WriteNonScatterPtr
|
STRB R9, [R13]
[ DummyReadFudge
[ FlpFlushPBI
LDRB R9, [R13, #4]
]
]
SUBS R12, R12, #1
ADDEQ R13, R13, #FlpDACK_TC_Offset
SUBS R10, R10, #1
......@@ -843,9 +841,9 @@ FlpWriteFIQ_BG ROUT
; Transfer the byte
STRB R9, [R13]
[ DummyReadFudge
[ FlpFlushPBI
LDRB R9, [R13, #4]
]
]
; Check for TC assertion next byte
SUBS R11, R11, #1
......@@ -1057,23 +1055,23 @@ FlpHandlerData ROUT
[ FloppyPCI
BL FlpDMATerminate
|
[ HAL
[ HAL
Push "R0-R3,R9,R12"
sbaddr R1, HAL_FIQDisableAll_routine
MOV LR, PC
LDMIA R1,{R9,PC}
Pull "R0-R3,R9,R12"
[ FloppyPodule
[ FloppyPodule
LDR LR, FlpDACK_TC
SUB LR, LR, #&400000
MOV R0, #0
STRB R0, [LR, #8]
]
|
]
|
MOV LR, #IOC ; LR-> IOC base address
ASSERT IOC :AND: &FF = 0
STRB LR, [LR, #IOCFIQMSK] ; Disable Data ReQuest FIQs
]
]
]
06 MOV LR, #0
......@@ -1396,8 +1394,8 @@ FlpHandlerData_ExecuteCommand
; Enable Data ReQuest FIQ's
[ :LNOT:HAL
MOV R1, #IOC ; R0-> IOC base address
MOV LR, #FlpDRQmask ; DRQ FIQ mask
MOV R1, #IOC ; R1-> IOC base address
MOV LR, #1:SHL:FlpDRQmask ; DRQ FIQ mask
STRB LR, [R1, #IOCFIQMSK] ; Enable Data ReQuest FIQs
]
| ; FloppyPCI
......@@ -2012,11 +2010,15 @@ FIQSetupWrite_BG ROUT
]
MOV PC, LR
FIQSetupVerify ROUT
[ FlpUseVerify
MOV R12, #0 ; No data transfer so implicitly none left
|
SUB R10, R10, #1
ADD R11, R12, R10
BIC R11, R11, R10 ; round up to sector boundary
SUB R11, R11, #1
SUB R13, R13, #FlpDACK_TC_Offset ; r13 now set
]
[ Debug10
MOV r1, #ScratchSpace
STMIA r1, {r8-r13}
......
......@@ -200,7 +200,6 @@ FlpInit ROUT
BL Configure37C665
|
[ HAL
[ {FALSE} ; IOMD HAL floppy support doesn't work yet. Disable it.
MOV r0, #9
MOV r1, #34<<8
SWI XOS_Memory
......@@ -209,19 +208,14 @@ FlpInit ROUT
MOVEQ r0, #MachHasNoFDC
STREQ r0, MachineID
BEQ %BT02
ADD r0, r1, #&3F0*4
ADD r0, r1, #&3F0 * 4
STR r0, FlpBase
ADD r0, r1, #&1A000
ADD r0, r1, #FlpDACK_Offset + FlpDACK_TC_Offset
STR r0, FlpDACK_TC
|
MOV R0, #MachHasNoFDC
STR R0, MachineID
B %BT02
]
|
LDR LR, =CnTbase + (&3F0 *4)
LDR LR, =CnTbase + (&3F0 * 4)
STR LR, FlpBase
LDR LR, =CnTbase + &1A000
LDR LR, =CnTbase + FlpDACK_Offset + FlpDACK_TC_Offset
STR LR, FlpDACK_TC
]
]
......@@ -438,6 +432,11 @@ Configure37C665 Entry "r0-r2"
FlpDoDCB ROUT
Push "LR"
[ {TRUE}
MOV R0, #256 ; For RPCEmu 0.8.9, the floppy controller is polled in a ratio
BL DoMicroDelay ; to CPU instruction decode. Going too fast prevents rom init.
; Burn 128us of CPU cycles during each of the power on DCBs.
]
BL FlpAddDCB ; Add DCB to queue (R1->R0,V)
10 LDR R0, [R1, #FlpDCBstatus] ; Get command error
CMPS R0, #FlpDCBpending ; DCB still pending?
......@@ -685,17 +684,8 @@ FlpReset ROUT
PHPSEI R1, R2 ; Disable IRQs
[ FloppyPCI
Push "R1,R3,R8,R9"
MOV R0, #FlpFintr
MOV R8, #0
MOV R9, #EntryNo_HAL_IRQEnable
SWI XOS_Hardware ; corrupts R0-R3
MOV R0, #FlpIndex
SWI XOS_Hardware ; corrupts R0-R3
Pull "R1,R3,R8,R9"
|
[ FloppyPodule
[ HAL
[ FloppyPodule
LDR R0, FlpDACK_TC
SUB R0, R0, #&600000
LDRB LR, [R0, #8]
......@@ -707,24 +697,26 @@ FlpReset ROUT
ORR LR, LR, #bit2
STRB LR, [R0, #8]
ASSERT FlpFintr = FlpIndex ; Following code results in a double enable
]
Push "R1,R3,R8,R9"
MOV R0, #13
MOV R8, #0
MOV R9, #EntryNo_HAL_IRQEnable
SWI XOS_Hardware ; corrupts R0-R3
Pull "R1,R3,R8,R9"
|
Push "R1,R3,R8,R9"
MOV R0, #IOMD_Floppy_DevNo
MOV R8, #0
MOV R0, #FlpFintr
MOV R8, #OSHW_CallHAL
MOV R9, #EntryNo_HAL_IRQEnable
SWI XOS_Hardware ; corrupts R0-R3
MOV R0, #IOMD_FloppyIndex_DevNo
MOV R8, #0
MOV R9, #EntryNo_HAL_IRQEnable
MOV R0, #FlpIndex
SWI XOS_Hardware ; corrupts R0-R3
Pull "R1,R3,R8,R9"
]
|
MOV R0, #IOC ; R0-> IOC registers
LDRB LR, [R0, #IOCIRQMSKB] ; Get IRQB mask bits
ORR LR, LR, #IOMD_floppy_IRQ_bit
STRB LR, [R0, #IOCIRQMSKB] ; Enable '765 FDC interrupts
LDRB LR, [R0, #IOCIRQMSKA] ; Get IRQA mask bits
ASSERT FlpIndex < 8 ; Index IRQ in IOC IRQA
ORR LR, LR, #1:SHL:FlpIndex ; Set Index pulse mask bit
STRB LR, [R0, #IOCIRQMSKA] ; Enable Index pulse interrupts
]
PLP R1
......
......@@ -178,6 +178,7 @@ InitEntry ROUT ; NO REENTRANCY CHECK NEEDED
STR R0, HAL_CounterDelay_routine+4
STR R1, HAL_CounterDelay_routine
[ :LNOT:FloppyPCI
MOV R9, #EntryNo_HAL_FIQDisableAll
SWI XOS_Hardware
BVS ErrXfree
......@@ -189,6 +190,7 @@ InitEntry ROUT ; NO REENTRANCY CHECK NEEDED
BVS ErrXfree
STR R0, HAL_FIQEnable_routine+4
STR R1, HAL_FIQEnable_routine
]
]
MOV R0,#6
......
......@@ -188,7 +188,7 @@ AddBusMasterChannel
; Register device
SUB r2, lr, #HALDevice_DMAL_Size + 4*1
MOV r0, r2
MOV r8, #2
MOV r8, #OSHW_DeviceAdd
SWI XOS_Hardware
BVS %FT90
......@@ -228,7 +228,7 @@ RegisterBusMaster
;
Entry "r8"
MOV r0, r6
MOV r8, #2
MOV r8, #OSHW_DeviceAdd
SWI XOS_Hardware
EXIT
......@@ -249,7 +249,7 @@ DeleteBusMaster
; Deregister the controller first -
; this should error if any of the channels are in use
MOV r0, r6
MOV r8, #3
MOV r8, #OSHW_DeviceRemove
SWI XOS_Hardware
EXIT VS
......
......@@ -12,18 +12,19 @@
; See the License for the specific language governing permissions and
; limitations under the License.
;
GBLL Dev
Dev SETL {FALSE}
;Debug message switches
GBLL Debug
[ Dev
Debug SETL {TRUE}
GBLL SpoolOff
SpoolOff SETL {FALSE} ;{TRUE} to disable spooling for debug messages
GBLL IrqDebug
GBLL Dev ; Development version or not
GBLL Debug ; To debug or not
GBLL SpoolOff ; True to disable SPOOL file around debug messages
GBLL IrqDebug ; True to skip debug if threaded in IRQ context
Dev SETL {FALSE}
[ Dev
Debug SETL {FALSE}
SpoolOff SETL {FALSE}
IrqDebug SETL {TRUE}
]
]
[ Debug
! 0, "*** WARNING *** DEBUG ON!"
]
......
......@@ -690,7 +690,7 @@ WinIDESetTimings
TEQ R7, #WinIDENoDevice
MOVEQ R2, #0
ADDNE R2, SP, #5*4+8
MOV R8, #0
MOV R8, #OSHW_CallHAL
MOV R9, #EntryNo_HAL_ATASetModes
[ Debug23
DREG R0,"Bus ",cc,Integer
......@@ -752,7 +752,7 @@ WinIDEDetectCableType ROUT
[ Debug23
DREG R0, "Cable of bus ",cc,Integer
]
MOV R8, #0
MOV R8, #OSHW_CallHAL
MOV R9, #EntryNo_HAL_ATACableID
SWI XOS_Hardware
TEQ R0, #0 ; If we see CBLID- line high
......@@ -1077,7 +1077,7 @@ WinIDESetDefaultTimings
MOV R0,R0,LSR #1
MOV R1,SP
ADD R2,SP,#8
MOV R8,#0
MOV R8,#OSHW_CallHAL
MOV R9,#EntryNo_HAL_ATASetModes
SWI XOS_Hardware
ADD SP,SP,#16
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment